CalibrationMPC5566 Microcontroller Reference Manual, Rev. 2B-4 Freescale SemiconductorB.3 Device-Specific InformationThe various address bus, data bus and bus control signals are sourced from different signals depending onthe MPC5500 device used, as detailed in the following sections.B.3.1 MPC5566 Calibration Bus ImplementationThe MPC5566 device has a set of external bus signals that are only used by the calibration bus. Thesedevice signals are prefixed by CAL, and their use does not affect the usage modes and electrical loadingon the equivalent signals for the EBI.B.4 Signals and PadsThe following sections detail the signal descriptions for the calibration bus.B.4.1 CAL_CS[0:3] — Calibration Chip Selects 0 through 3CAL_CS[n] is asserted by the master to indicate that this transaction is targeted for a particular calibrationmemory bank.The calibration chip selects are driven by the EBI. CAL_CS[n] is driven in the same clock as the assertionof TS and valid address, and is kept valid until the cycle is terminated. Bus timing is identical to standardEBI timing.B.4.1.1 Number of Chip Selects and Maximum Memory SizeThe trade-off between calibration chip selects and address lines is the same as the trade-off betweennon-calibration chip selects and address lines for the 324 pin package.B.4.2 Pad RingThis section provides a list of the calibration pins and associated pad configuration registers (PCRs),including links to the detailed PCR information for each pin or pin group.Refer to Table B-1 for device signal names.Table B-2. Maximum Memory Size According to Calibration Chip SelectsMaximum Memory Allocated for CalibrationDevice 0 Device 2 Device 3CAL_CS[0] only 4 MB — —CAL_CS[0] andCAL_CS[2]2 MB 2 MB —CAL_CS[0] andCAL_CS[2:3]1 MB 1 MB 1 MB
