Enhanced Direct Memory Access (eDMA)MPC5566 Microcontroller Reference Manual, Rev. 29-36 Freescale SemiconductorFigure 9-26. eDMA Operation, Part 39.3.3 eDMA PerformanceThis section addresses the performance of the eDMA module, focusing on two separate metrics. In thetraditional data movement context, performance is best expressed as the peak data transfer rates achievedusing the eDMA. In most implementations, this transfer rate is limited by the speed of the source anddestination address spaces. In a second context where device-paced movement of single data valuesto/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a moreuseful metric. In this environment, the speed of the source and destination address spaces remainsimportant, but the microarchitecture of the eDMA also factors significantly into the resulting metric.The peak transfer rates for several different source and destination transfers are shown in Table 9-20. Thefollowing assumptions apply to Table 9-20 and Table 9-21:• Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase.• All slave reads require two wait-states, and slave writes three wait-states, again viewed from thesystem bus data phase.• All slave accesses are 32-bits in size.Slave InterfaceeDMAeDMA DoneSystem BusSlave Write DataSlave Write AddressBus Write DataSlave Read DataBus AddresseDMA EngineTCD0TCDn-1*eDMA PeripheralBus Read DataRequestSRAMTransfer Control Descriptor(TCD)SRAMData Path AddressPath ControlProgram Model/Channel Arbitration*n = 64 channels
