Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 11-23LOCKS status bits are negated. While the FMPLL is in an unlocked condition, the system clocks continueto be sourced from the FMPLL as the FMPLL attempts to re-lock. Consequently, during the re-lockingprocess, the system clock frequency is not well defined and can exceed the maximum system frequencythereby violating the system clock timing specifications (when changing MFD and PREDIV, this isavoided by following the procedure detailed in Section 11.4.3, “Clock Configuration”). Because thiscondition can arise during unexpected loss of lock events, it is recommended to use the loss of lock resetfunctionality, Refer to Section 11.4.2.5.1, “FMPLL Loss-of-Lock Reset,” below. However, LOLRE mustbe cleared while changing the MFD otherwise a reset occurs.After the FMPLL has relocked, the LOCK bit is set. The LOCKS bit remains cleared if the loss of lockwas unexpected. The LOCKS bit is set to 1 when the loss of lock was caused by changing the MFD.11.4.2.5.1 FMPLL Loss-of-Lock ResetThe FMPLL provides the ability to assert reset when a loss of lock condition occurs by programming theFMPLL_SYNCR[LOLRE] bit. Reset is asserted if LOLRE is set and loss of lock occurs. Because theFMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS] bits are reinitialized after reset, the system resetstatus register (SIU_RSR) must be read to determine that a loss of lock condition occurred.To exit reset, the reference must be present and the FMPLL must acquire lock. In bypass mode, the FMPLLcannot lock. Therefore a loss of lock condition cannot occur, and LOLRE has no effect.11.4.2.5.2 FMPLL Loss-of-Lock Interrupt RequestThe FMPLL provides the ability to request an interrupt when a loss of lock condition occurs byprogramming the FMPLL_SYNCR[LOLIRQ] bit. An interrupt is requested by the FMPLL if LOLIRQ isset and loss of lock occurs.In bypass mode, the FMPLL cannot lock. Therefore a loss of lock condition cannot occur, and the LOLIRQbit has no effect.11.4.2.6 Loss-of-Clock DetectionThe FMPLL continuously monitors the reference and feedback clocks. In the event either of the clocks fallbelow a threshold frequency, the system reports a loss of clock condition. You can enable a feature to havethe FMPLL switch the system clocks to a backup clock in the event of such a failure. Additionally, youcan enter a system RESET, assert an interrupt request, or do nothing if the FMPLL reports this condition.11.4.2.6.1 Alternate and Backup Clock SelectionIf the user enables loss of clock by setting FMPLL.SYNCR[LOCEN] = 1, then the FMPLL transitionssystem clocks to a backup clock source in the event of a clock failure as per Table 11-8.If loss of clock is enabled and the reference clock is the source of the failure, the FMPLL enters self-clockmode (SCM). The exact frequency during self-clock mode operation is indeterminate due to process,voltage, and temperature variation but is guaranteed to be below the maximum system frequency. If theFMPLL clocks have failed, the FMPLL transitions the system clock source to the reference clock.
