Enhanced Direct Memory Access (eDMA)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 9-39entry – channel startup (four cycles)read_ws – wait states seen during the system bus read data phasewrite_ws – wait states seen during the system bus write data phaseexit – channel shutdown (three cycles)For example: consider a system with the following characteristics:• Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase.• All slave reads require two wait-states, and slave writes three wait-states, again viewed from thesystem bus data phase.• System operates at 150 MHz.For an SRAM to slave transfer,PEAKreq = 150 MHz / [4 + (1 + 1) + (1 + 3) + 3] cycles = 11.5 Mreq/secFor an slave to SRAM transfer,PEAKreq = 150 MHz / [4 + (1 + 2) + (1 + 1) + 3] cycles = 12.5 Mreq/secAssuming an even distribution of the two transfer types, the average peak request rate is:PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/secThe minimum number of cycles to perform a single read/write, zero wait states on the system bus, from acold start (no channel is executing, eDMA is idle) are the following:• 11 cycles for a software (TCD.START bit) request• 12 cycles for a hardware (eDMA peripheral request signal) requestTwo cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting fromthe internal registering of the eDMA peripheral request signals. For the peak request rate calculationsabove, the arbitration and request registering is absorbed in or overlap the previous executing channel.NOTEWhen channel linking or scatter/gather is enabled, a two-cycle delay isimposed on the next channel selection and startup. This allows the linkchannel or the scatter/gather channel to be eligible and considered in thearbitration pool for next channel selection.9.4 Initialization and Application Information9.4.1 eDMA InitializationA typical initialization of the eDMA has the following sequence:1. Write the EDMA_CR if a configuration other than the default is desired.2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than thedefault is desired.3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers (optional).
