External Bus Interface (EBI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 12-1112.2.1.15 Transfer Size 0 through 1 (TSIZ[0:1])TSIZ[0:1] indicates the size of the requested data transfer. TSIZ[0:1] is driven by the EBI or an externalmaster depending on which component controls the external bus. The TSIZ[0:1] signals can be used withADDR[30:31] to determine which byte lanes of the data bus are involved in the transfer. For non-bursttransfers, the TSIZ[0:1] signals specify the number of bytes starting from the byte location addressed byADDR[30:31]. In burst transfers, the value of TSIZ[0:1] is always 00.If the SIZEN bit in the EBI_MCR is 1, then TSIZ[0:1] is ignored by the EBI as an input for external mastertransactions and the size is instead determined by the SIZE field in the EBI_MCR. The SIZEN bit has noeffect on the EBI when it is mastering a transaction on the external bus. TSIZ[0:1] is still driven by the EBIand is used by the external master depending on the SIZEN setting for the external master’s EBI. SeeSection 12.3.1.3, “EBI Module Configuration Register (EBI_MCR).”12.2.1.16 Calibration Chip Selects (CAL_CS[0:3])CAL_CS[n] is asserted by the master to indicate that this transaction is targeted for a particular memorybank on the calibration external bus.The calibration chip selects are driven only by the EBI. External master accesses on the calibration bus arenot supported. In all other aspects, the calibration chip selects behave exactly as the primary chip selects.See Section 12.4.1.5, “Memory Controller with Support for Various Memory Types” for details on chipselect operation.12.2.1.17 Calibration SignalsThe calibration signal functions are explained in Chapter 2, “Signal Description.”DATA is not driven by the EBI during a calibration bus access. During a calibration bus access, thenon-calibration bus signals (other than DATA) are held in a negated state, with the exception of RD_WRand ADDR, which reflect the same values shown on the calibration version of those signals. Because theTS and CS signals are held negated on the non-calibration bus during calibration accesses, no transferoccurs on the EBI.During an EBI bus access, the calibration bus signals (other than CAL_DATA) are held in a negated state.CAL_DATA is not driven during non-calibration accesses.Table 12-4. TSIZ[0:1] EncodingBurst Cycle TSIZ[0:1] Transfer SizeN 01 8-bitN 10 16-bitN 11 Invalid valueN 00 32-bitY 00 Burst
