Deserial Serial Peripheral Interface (DSPI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 20-1120.3.2.2 DSPI Transfer Count Register (DSPIx_TCR)The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counteris intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI isrunning.20CLR_TXFClear TX FIFO. Flushes the TX FIFO. Write a 1 to the CLR_TXF bit to clear the TX FIFO counter. TheCLR_TXF bit is always read as zero.0 Do not clear the TX FIFO counter1 Clear the TX FIFO counter21CLR_RXFClear RX FIFO. Flushes the RX FIFO. Write a 1 to the CLR_RXF bit to clear the RX counter. The CLR_RXFbit is always read as zero.0 Do not clear the RX FIFO counter1 Clear the RX FIFO counter22–23SMPL_PT[0:1]Sample point. Allows the host software to select when the DSPI master samples SIN in modified transferformat. Figure 20-36 shows where the master can sample the SIN pin. The following table lists the delayedsample points.24–30 Reserved31HALTHalt. Provides a mechanism for software to start and stop DSPI transfers.See Section 20.4.2, “Start and Stop of DSPI Transfers,” for details on the operation of this bit.0 Start transfers1 Stop transfersTable 20-3. DSPIx_MCR Field Descriptions (continued)Field DescriptionSMPL_PT Number of system clock cycles betweenodd-numbered edge of SCK[x] and sampling of SIN[x].00 001 110 211 Invalid value
