Enhanced Modular Input/Output Subsystem (eMIOS)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 17-2917.4.4.4.1 General Purpose Input/Output Mode (GPIO)The following table lists the general purpose input/output mode settings:In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter(EMIOS_CCNTRn register) is cleared and disabled. All control bits remain accessible. To prepare the UCfor a new operating mode, writing to registers EMIOS_CADRn or EMIOS_CBDRn stores the same valuein registers A1/A2 or B1/B2, respectively.MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.It is required that when changing MODE[0:6], the application software goes to GPIO mode first to resetthe UC’s internal functions properly. Failure to do this can lead to invalid and unexpected output comparesand input capture results, or can cause the FLAGs to be set incorrectly.In GPIO input mode, the FLAG generation is determined according to EDPOL and EDSEL bits and theinput pin status can be determined by reading the UCIN bit.In GPIO output mode, the unified channel is used as a single output port pin and the value of the EDPOLbit is permanently transferred to the output flip-flop.NOTEThe GPIO modes provided in the eMIOS are particularly useful as interimmodes when certain other eMIOS modes are being dynamically configuredand enabled or disabled during the execution of the application. For normalGPIO function on the eMIOS pins, it is recommended that the SIU be usedto configure those pins as system GPIO. See Section 6.2.1.3,“General-Purpose I/O (GPIO[0:213])” pins.17.4.4.4.2 Single-Action Input Capture Mode (SAIC)The following table lists the single action input capture mode settings:In SAIC mode, when a triggering event occurs on the input pin, the value on the selected time base iscaptured into register A2. At the same time, the FLAG bit is set to indicate that an input capture hasoccurred. Register EMIOS_CADRn returns the value of register A2.The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOLand EDSEL bits in EMIOS_CCRn.Table 17-14. GPIO Operating ModeMODE[0:6] Unified Channel GPIO Operating Mode0b0000000 General purpose input/output mode (input)0b0000001 General purpose input/output mode (output)Table 17-15. SAIC Operating ModeMODE[0:6] Unified Channel SAIC Operating Mode0b0000010 Single action input capture mode
