Crossbar Switch (XBAR)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 7-37.1.4 Modes of Operation7.1.4.1 Normal ModeIn normal mode, the XBAR provides the register interface and logic that controls crossbar switchconfiguration.7.1.4.2 Debug ModeThe XBAR operation in debug mode is identical to operation in normal mode.7.2 Memory Map and Register DefinitionThe memory map for the XBAR program-visible registers is shown in Table 7-2.Table 7-2. XBAR Register Memory MapAddress Register Name Register Description BitsBase = 0xFFF0_4000 XBAR_MPR0 Master priority register for slave port 0 32Base + (0x0004–0x000F) — Reserved —Base + 0x0010 XBAR_SGPCR0 General-purpose control register for slave port 0 32Base + (0x0014–0x00FF) — Reserved —Base + 0x0100 XBAR_MPR1 Master priority register for slave port 1 32Base +(0x0104–0x010F) — Reserved —Base + 0x0110 XBAR_SGPCR1 General-purpose control register for slave port 1 32Base + (0x0114–0x02FF) — Reserved —Base + 0x0300 XBAR_MPR3 Master priority register for slave port 3 32Base + (0x0304–0x030F) — Reserved —Base + 0x0310 XBAR_SGPCR3 General-purpose control register for slave port 3 32Base + (0x0314–0x05FF) — Reserved —Base + 0x0600 XBAR_MPR6 Master priority register for slave port 6 32Base + (0x0604–0x060F) — Reserved —Base + 0x0610 XBAR_SGPCR6 General-purpose control register for slave port 6 32Base + (0x0614–0x06FF) — Reserved —Base + 0x0700 XBAR_MPR7 Master priority register for slave port 7 32Base + (0x0704–0x070F) — Reserved —Base + 0x0710 XBAR_SGPCR7 General-purpose control register for slave port 7 32Base + 0x0714–0x0003_FFFF — Reserved —
