Enhanced Serial Communication Interface (eSCI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 21-9NOTESIn 8-bit data format, only bits 8–15 of ESCIx_DR need to be accessed.When transmitting in 9-bit data format and using 8-bit write instructions,write first to ESCIx_DR[0–7], then ESCIx_DR[8–15]. For 9-bittransmissions, a single write can also be used.Do not use ESCIx_DR in LIN mode, writes to this register are blocked inLIN mode.Even if parity generation/checking is enabled via ESCIx_CR[PE], the paritybit is not masked out.21.3.3.4 eSCI Status Register (ESCIx_SR)The ESCIx_SR indicates the current status. The status flags can be polled, and some can also be used togenerate interrupts. All bits in ESCIx_SR except for RAF are cleared by writing 1 to them.Table 21-5. ESCIx_DR Field DescriptionField Description0R8Received bit 8. R8 is the ninth data bit received when the eSCI is configured for 9-bit data format (M = 1).1T8Transmit bit 8. T8 is the ninth data bit transmitted when the eSCI is configured for 9-bit data format (M = 1).Note: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same valueis transmitted until T8 is rewritten.2–7 Reserved.8–15R7–R0T7–T0Received bits/transmit bits 7–0 for 9-bit or 8-bit formats. Bits 7–0 from SCI communication can be read fromESCIx_DR[8–15] (provided that SCI communication was successful). Writing to ESCIx_DR [8–15] provides bits 7–0for SCI transmission.Address: Base + 0x0008 Access: R/W1c0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R TDRE TC RDRF IDLE OR NF FE PF 0 0 0 BERR 0 0 0 RAFW w1c w1c w1c w1c w1c w1c w1c w1c w1cReset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R RXRDYTXRDY LWAKE STO PBERR CERR CKERR FRC 0 0 0 0 0 0 0 OVFLW w1c w1c w1c w1c w1c w1c w1c w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 21-5. eSCI Status Register (ESCIx_SR)
