IEEE 1149.1 Test Access Port Controller (JTAGC)MPC5566 Microcontroller Reference Manual, Rev. 224-6 Freescale Semiconductor24.4 Functional Description24.4.1 JTAGC Reset ConfigurationWhile in reset, the TAP controller is forced into the test-logic-reset state, thus disabling the test logic andallowing normal operation of the on-chip system logic. In addition, the instruction register is loaded withthe IDCODE instruction.24.4.2 IEEE 1149.1-2001 (JTAG) Test Access PortThe JTAGC uses the IEEE 1149.1-2001 TAP for accessing registers. This port can be shared with otherTAP controllers on the MCU. Ownership of the port is determined by the value of the JCOMP signal andthe currently loaded instruction. For more detail on TAP sharing via JTAGC instructions refer toSection 24.4.4.2, “ACCESS_AUX_TAP_x Instructions.”Data is shifted between TDI and TDO though the selected register starting with the least significant bit, asillustrated in Figure 24-4. This applies for the instruction register, test data registers, and the bypassregister.Figure 24-4. Shifting Data Through a Register24.4.3 TAP Controller State MachineThe TAP controller is a synchronous state machine that interprets the sequence of logical values on theTMS pin. Figure 24-5 shows the machine’s states. The value shown next to each state is the value of theTMS signal sampled on the rising edge of the TCK signal.As Figure 24-5 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of risingedges also causes the state machine to enter the test-logic-reset state.Selected registerMSB LSBTDI TDO
