IntroductionMPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 1-15priority level can be raised temporarily so that no task can preempt another task that shares the sameresource.Multiple processors can assert interrupt requests to each other through software settable interrupt requests(by using application software to assert requests). These maskable interrupt requests can divide thesoftware into a high-priority portion and a low-priority portion for servicing the interrupt requests. Thehigh-priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a softwaresettable interrupt request to finish the servicing in a lower priority ISR.1.5.5 Frequency Modulated Phase-Locking Loop (FMPLL)The frequency modulated phase-locking loop (FMPLL) generates high-speed system clocks from an8–20 MHz crystal oscillator or an external clock generator. Furthermore, the FMPLL supportsprogrammable frequency modulation of the system clock. The PLL multiplication factor, output clockdivider ratio, modulation depth, and modulation rate are all software configurable.1.5.6 External Bus Interface (EBI)The external bus interface (EBI) controls data transfer across the crossbar switch to/from memories orperipherals in the external address space. The EBI is available on the 416 BGA package only. The EBI alsoenables an external master to access internal address space. The EBI includes a memory controller thatgenerates interface signals to support a variety of external memories. The memory controller supportssingle data rate (SDR) burst mode flash, external SRAM, and asynchronous memories. In addition, theEBI supports up to four regions (via chip selects), along with programmed region-specific attributes.1.5.7 System Integration Unit (SIU)The device’s system integration unit (SIU) controls MCU reset configuration, pad configuration, externalinterrupt, general-purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation.The reset configuration module contains the external pin boot configuration logic. The pad configurationmodule controls the static electrical characteristics of I/O pins. The GPIO module provides uniform anddiscrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoringof internal and external reset sources, and drives the RSTOUT pin. The SIU is accessed by the e200z6 corethrough the crossbar switch.1.5.8 Error Correction Status Module (ECSM)The error correction status module (ECSM) provides status information regarding platform memory errorsreported by error-correcting codes.1.5.9 Flash MemoryThe MPC5566 provides 3 MB of programmable, non-volatile, flash memory storage. Non-volatilememory (NVM) can be used for instruction and/or data storage.
