Flash MemoryMPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 13-2513.4.1.9 FBIU Per-Master Prefetch TriggeringPrefetch triggering can be controlled for individual bus masters. System bus accesses indicate therequesting master.13.4.1.10 FBIU Buffer InvalidationThe line read buffers can be invalidated under hardware and software control. Buffers are automaticallyinvalidated whenever the buffers are turned on or off, or at the beginning of a program or erase operation.NOTEDisable prefetching before invalidating the buffers. This includes starting aprogram or erase operation, or turning on and off the buffers.13.4.1.11 Flash Wait-state EmulationEmulation of other memory array timings are supported by the Flash BIU. This functionality can be usefulto maintain the access timing for blocks of memory which were used to overlay flash blocks for thepurpose of system calibration or tuning during code development.The Flash BIU inserts additional primary wait states according to user-programmable values for primarywait states. When these inputs are non-zero, additional cycles are added to system bus transfers. Normalsystem bus termination is extended. In addition, no line read buffer prefetches are initiated, and buffer hitsare ignored.13.4.2 Flash Memory Array: User ModeIn user (normal) operating mode the flash module can be read, written (register writes and interlockwrites), programmed, or erased. The following subsections define all actions that can be performed innormal operating mode. The registers mentioned in these sections are detailed in Section 13.3.2, “RegisterDescriptions.”13.4.2.1 Flash Read and WriteThe default state of the flash module is read. The main and shadow address space can be read only in theread state. The module configuration register (FLASH_MCR) is always available for read. The flashmodule enters the read state on reset. The flash module is in the read state under four sets of conditions:• The read state is active when FLASH_MCR[STOP] = 0 (user mode read).• The read state is active when FLASH_MCR[PGM] = 1 and/or FLASH_MCR[ERS] = 1 and highvoltage operation is ongoing (read while write).NOTEReads done to the partitions being operated on (either erased orprogrammed) result in an errors and the FLASH_MCR[RWE] bit is set.
