Fast Ethernet Controller (FEC)MPC5566 Microcontroller Reference Manual, Rev. 215-38 Freescale SemiconductorFigure 15-29. Ethernet Address Recognition—Microcode Decisions15.4.9 Hash AlgorithmThe hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bitdestination address is mapped into one of 64 bits, which are represented by 64 bits stored in GAUR, GALR(group address hash match) or IAUR, IALR (individual address hash match). This mapping is performedby passing the 48-bit address through the on-chip 32-bit CRC generator and selecting the 6 mostsignificant bits of the CRC-encoded result to generate a number between 0 and 63. The MSB of the CRCresult selects GAUR (MSB = 1) or GALR (MSB = 0). The least significant 5 bits of the hash result selectthe bit within the selected register. If the CRC generator selects a bit that is set in the hash table, the frameis accepted; otherwise, it is rejected.For example, if eight group addresses are stored in the hash table and random group addresses are received,the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory.Those that do reach memory must be further filtered by the processor to determine if they truly containone of the eight desired addresses.The effectiveness of the hash table declines as the number of addresses increases.Receive AddressI/G Address?Exact Match?Hash SearchGroup TableMatch?Hash SearchIndividual TableFalseMatch?False FalseTrue TrueTrueNOTES:FCE - field in RCR register (Flow Control Enable)I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)IndividualGroupTrueFalseTrueFalse?Pause AddressFCE?RecognitionReject FrameFlush from FIFOReject FrameFlush from FIFO Receive FrameReceive FrameReceive FrameReceive Frame
