Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)MPC5566 Microcontroller Reference Manual, Rev. 211-16 Freescale Semiconductor11.3.1.2 Synthesizer Status Register (FMPLL_SYNSR)The synthesizer status register (FMPLL_SYNSR) is a 32-bit register. Only the LOLF and LOCF flag bitsare writable in this register. Writes to bits other than the LOLF and LOCF have no effect.20–21DEPTH[0:1]Controls the frequency modulation depth and enables the frequency modulation. When programmed to avalue other than 0x0, the frequency modulation is automatically enabled. The programmable frequencydeviations from the system frequency are shown below. If the depth is changed to a value other than 0x0,the calibration sequence is reinitialized.Note: To prevent unintentional interrupt requests, clear LOLIRQ before changing DEPTH.22–31EXP[0:9]Expected difference value. Holds the expected value of the difference of the reference and the feedbackcounters. Refer to Section 11.4.3.3, “FM Calibration Routine” to determine the value of these bits. This fieldis written by the application before entering calibration mode.Address: Base + 0x0004 Access: User R/W0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0 0 0 0 0 LOLF LOC MODE PLLSELPLLREF LOCKS LOCK LOCF CALDONECALPASSW w1c w1cReset 0 0 0 0 0 0 0 0 — 1 —1 —1 —1 —2 0 0 01 Reset state determined during reset configuration. (Refer to Section 11.1.4, “FMPLL Modes of Operation,” for moreinformation.)2 Reset state determined during reset.Note: “w1c” signifies that this bit is cleared by writing a 1 to it.Figure 11-9. Synthesizer Status Register (FMPLL_SYNSR)Table 11-4. FMPLL_SYNCR Field Descriptions (continued)Field DescriptionDEPTH[1] DEPTH[0] Modulation Depth (% of Fsys)0 0 00 1 1.0 ± 0.21 0 2.0 ± 0.21 1 Reserved
