Enhanced Serial Communication Interface (eSCI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 21-37It is possible to set up a DMA channel to handle all the tasks required to send a TX frame. For thisoperation, the TX DMA channel must be activated by setting the ESCIx_CR2[TXDMA] bit. The controlinformation for the LIN frame (ID, message length, TX/RX type, timeout, etc.) and the data bytes arestored at an appropriate memory location. The DMA controller is then set up to transfer this block ofmemory to a location (the ESCIx_LTR). After transmission is complete, either the DMA controller or theLIN hardware can generate an interrupt to the CPU.NOTEIn contrast to the standard software implementation where each bytetransmission requires several interrupts, the DMA controller and eSCIhandle communication, bit error and physical bus error checking,checksum, and CRC generation (checking on the RX side).Refer to Figure 21-25 for more information.Figure 21-25. DMA Transfer of a TX Frame21.4.10.3 Generating an RX FrameFor RX frames the header information is provided by the LIN master. The data, CRC and checksum bytes(as enabled) are provided by the LIN slave. The LIN master verifies CRC and checksum bytes transmittedby the slave.For an RX frame, control information must be written to the ESCIx_LTR in the same manner as for theTX frames. Additionally the timeout bits, which define the time to complete the entire frame, must bewritten. Then the ESCIx_SR[RXRDY] bit must be checked (either with an interrupt, RX DMA interface,or by polling) to detect incoming data bytes. The checksum byte normally does not appear in theESCIx_LRR, instead the LIN hardware verifies the checksum and issue an interrupt, if the checksum valueis not correct.Two DMA channels can be used when executing an RX frame: one to transfer the header/controlinformation from a memory location to the ESCIx_LTR, and one to transfer the incoming data bytes fromthe ESCIx_LRR to a table in memory. After the last byte from the RX frame has been stored, the DMAcontroller can indicate completion to the CPU.Break Sync ID Data Data CSum• • •LIN FrameLIN eSCIESCIx_LTRDMAControllerData nData 1Control/TimeoutLengthID••• TX DMAChannel
