Flash MemoryMPC5566 Microcontroller Reference Manual, Rev. 213-24 Freescale Semiconductor13.4.1.7 FBIU Line Read Buffers and Prefetch OperationThe Flash BIU contains a pair of 256-bit line read buffers which are used to hold data read from the flasharray. Each buffer operates independently and is filled using a single array access. The buffers are used forboth prefetch and normal demand fetches.Prefetch triggering is controllable on a per-master and access-type basis. Bus masters can be enabled ordisabled from triggering prefetches, and triggering can be further restricted based on whether a read accessis for instruction or data and whether or not it is a burst access. A read access to the Flash BIU can triggera prefetch to the next sequential line of array data on the cycle following the request. The access addressis incremented to the next-higher 32-byte boundary, and a flash array prefetch is initiated if the data is notalready resident in a line read buffer. Prefetched data is loaded into the buffer which is not being used tosatisfy the original request.Buffers can be in one of six states, listed here in prioritized order:• Invalid—the buffer contains no valid data.• Used—the buffer contains valid data which has been provided to satisfy a burst type read.• Valid—the buffer contains valid data which has been provided to satisfy a single type read.• Prefetched—the buffer contains valid data which has been prefetched to satisfy a potential futureaccess.• Busy—the buffer is currently being used to satisfy a burst read.• Busy fill—the buffer has been allocated to receive data from the flash array, and the array accessis still in progress.Selection of a buffer to fill on a buffer miss is based on this prioritized order beginning with the first item(invalid). Selection of a buffer to fill on a triggered prefetch is based on the buffer which is not being usedto satisfy the triggering access.The consequences of this replacement policy are that buffers are selected for filling on a ‘least recentlyupdated’ basis when prefetching, and on a ‘most recently emptied’ basis for demand fetches (that is, a fetchwhich is actually satisfying a current system bus access). This policy allows for prefetched data to remainvalid when non-prefetch enabled bus masters are granted flash access.Several algorithms are available for prefetch control which trade off performance for power. They aredescribed in Section 13.3.2.8, “Flash Bus Interface Unit Control Register (FLASH_BIUCR).” Moreaggressive prefetching increases power due to the number of wasted (discarded) prefetches, but canincrease performance by lowering average read latency.13.4.1.8 FBIU Instruction/Data Prefetch TriggeringPrefetch triggering can be enabled for instruction reads. Triggering can be enabled for all instruction readsor only for instruction burst reads. Prefetch triggering can be enabled for data reads. Triggering can beenabled for all data reads or only for data burst reads. Prefetches are not triggered by write cycles.
