NXP Semiconductors MKL27Z128VFM4 manuals
MKL27Z128VFM4
Table of contents
- Table Of Contents
- Table Of Contents
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- Table Of Contents
- Table Of Contents
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- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
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- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Overview
- Typographic notation
- Module functional categories
- ARM Cortex-M0+ core modules
- Memories and memory interfaces
- Security and integrity modules
- Communication interfaces
- Human-machine interfaces
- Analog reference options
- ARM Cortex-M0+ core introduction
- Core privilege levels
- AWIC introduction
- Introduction
- Flash memory map
- FTFA_FOPT register
- SRAM retention in low power modes
- System memory map
- Bit Manipulation Engine
- Read-after-write sequence and required serialization of memory operations
- Clock definitions
- Device clock summary
- Internal clocking requirements
- Clock divider values after reset
- Clock gating
- PMC 1-kHz LPO clock
- RTC clocking
- LPTMR clocking
- TPM clocking
- LPUART clocking
- FlexIO clocking
- Power-on reset (POR)
- MCU resets
- RESET pin
- Boot sources
- Boot sequence
- DMA Wakeup
- Compute Operation
- Peripheral Doze
- Entering and exiting power modes
- Module operation in low-power modes
- Debug
- SWD status and control registers
- MDM-AP Control Register
- MDM-AP Status Register
- Debug resets
- Debug in low-power modes
- Debug and security
- KL27 Family Pinouts
- Module Signal Description Tables
- System modules
- Timer Modules
- Human-machine interfaces (HMI)
- Chip-specific PORT information
- Port control and interrupt summary
- Modes of operation
- External signal description
- Pin Control Register n (PORTx_PCRn)
- Global Pin Control Low Register (PORTx_GPCLR)
- Interrupt Status Flag Register (PORTx_ISFR)
- Global pin control
- Chip-specific SIM information
- Memory map and register definition
- System Options Register 1 (SIM_SOPT1)
- SOPT1 Configuration Register (SIM_SOPT1CFG)
- System Options Register 2 (SIM_SOPT2)
- System Options Register 4 (SIM_SOPT4)
- System Options Register 5 (SIM_SOPT5)
- System Options Register 7 (SIM_SOPT7)
- System Device Identification Register (SIM_SDID)
- System Clock Gating Control Register 4 (SIM_SCGC4)
- System Clock Gating Control Register 5 (SIM_SCGC5)
- System Clock Gating Control Register 6 (SIM_SCGC6)
- System Clock Gating Control Register 7 (SIM_SCGC7)
- Flash Configuration Register 1 (SIM_FCFG1)
- Flash Configuration Register 2 (SIM_FCFG2)
- Unique Identification Register Mid-High (SIM_UIDMH)
- Unique Identification Register Mid Low (SIM_UIDML)
- COP Control Register (SIM_COPC)
- Service COP (SIM_SRVCOP)
- COP watchdog operation
- Chip-Specific Information
- Functional Description
- The Kinetis Bootloader Configuration Area (BCA)
- Start-up Process
- Clock Configuration
- Bootloader Entry Point
- Bootloader Protocol
- Bootloader Packet Types
- Bootloader Command API
- Bootloader Exit state
- Peripherals Supported
- SPI Peripheral
- USB peripheral
- Get/SetProperty Command Properties
- Property Definitions
- Kinetis Bootloader Status Error Codes
- Bootloader errata
- Chip-specific SMC information
- Memory map and register descriptions
- Power Mode Protection register (SMC_PMPROT)
- Power Mode Control register (SMC_PMCTRL)
- Stop Control Register (SMC_STOPCTRL)
- Power Mode Status register (SMC_PMSTAT)
- Power mode entry/exit sequencing
- Run modes
- Wait modes
- Stop modes
- Debug in low power modes
- LVD reset operation
- I/O retention
- Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)
- Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)
- Regulator Status And Control register (PMC_REGSC)
- Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
- Platform Control Register (MCM_PLACR)
- Compute Operation Control Register (MCM_CPO)
- Chip-specific AXBS-Lite information
- Features
- Arbitration
- Initialization/application information
- LLWU interrupt
- Block diagram
- LLWU signal descriptions
- LLWU Pin Enable 1 register (LLWU_PE1)
- LLWU Pin Enable 2 register (LLWU_PE2)
- LLWU Pin Enable 3 register (LLWU_PE3)
- LLWU Pin Enable 4 register (LLWU_PE4)
- LLWU Module Enable register (LLWU_ME)
- LLWU Flag 1 register (LLWU_F1)
- LLWU Flag 2 register (LLWU_F2)
- LLWU Flag 3 register (LLWU_F3)
- LLWU Pin Filter 1 register (LLWU_FILT1)
- LLWU Pin Filter 2 register (LLWU_FILT2)
- LLS mode
- Chip-specific AIPS-Lite information
- General operation
- Peripheral Access Control Register (AIPS_PACRn)
- Chip-specific DMAMUX information
- DMA transfers via PIT trigger
- DMA channels with periodic triggering capability
- DMA channels with no triggering capability
- Always-enabled DMA sources
- DMA Transfer Overview
- Memory Map/Register Definition
- Source Address Register (DMA_SARn)
- Destination Address Register (DMA_DARn)
- DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
- DMA Control Register (DMA_DCRn)
- Channel initialization and startup
- Dual-Address Data Transfer Mode
- Termination
- System Reset Status Register 0 (RCM_SRS0)
- System Reset Status Register 1 (RCM_SRS1)
- Reset Pin Filter Control register (RCM_RPFC)
- Reset Pin Filter Width register (RCM_RPFW)
- Force Mode Register (RCM_FM)
- Sticky System Reset Status Register 0 (RCM_SSRS0)
- Sticky System Reset Status Register 1 (RCM_SSRS1)
- Chip-specific ADC information
- DMA Support on ADC
- ADC analog supply and reference connections
- ADC signal descriptions
- Analog Channel Inputs (ADx)
- ADC Status and Control Registers 1 (ADCx_SC1n)
- ADC Configuration Register 1 (ADCx_CFG1)
- ADC Configuration Register 2 (ADCx_CFG2)
- ADC Data Result Register (ADCx_Rn)
- Compare Value Registers (ADCx_CVn)
- Status and Control Register 2 (ADCx_SC2)
- Status and Control Register 3 (ADCx_SC3)
- ADC Offset Correction Register (ADCx_OFS)
- ADC Plus-Side Gain Register (ADCx_PG)
- ADC Plus-Side General Calibration Value Register (ADCx_CLPD)
- ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
- ADC Plus-Side General Calibration Value Register (ADCx_CLP3)
- ADC Plus-Side General Calibration Value Register (ADCx_CLP1)
- ADC Minus-Side General Calibration Value Register (ADCx_CLMD)
- ADC Minus-Side General Calibration Value Register (ADCx_CLM4)
- ADC Minus-Side General Calibration Value Register (ADCx_CLM2)
- ADC Minus-Side General Calibration Value Register (ADCx_CLM0)
- Clock select and divide control
- Voltage reference selection
- Conversion control
- Automatic compare function
- Calibration function
- User-defined offset function
- Temperature sensor
- MCU wait mode operation
- MCU Low-Power Stop mode operation
- Initialization information
- Application information
- Sources of error
- Chip-specific CMP information
- CMP external references
- bit DAC key features
- CMP, DAC and ANMUX diagram
- CMP block diagram
- Memory map/register definitions
- CMP Control Register 1 (CMPx_CR1)
- CMP Filter Period Register (CMPx_FPR)
- CMP Status and Control Register (CMPx_SCR)
- DAC Control Register (CMPx_DACCR)
- CMP functional modes
- Power modes
- Startup and operation
- Low-pass filter
- CMP interrupts
- Digital-to-analog converter
- Voltage reference source select
- DAC Data Low Register (DACx_DATnL)
- DAC Status Register (DACx_SR)
- DAC Control Register (DACx_C0)
- DAC Control Register 1 (DACx_C1)
- DMA operation
- VREF Signal Descriptions
- VREF Trim Register (VREF_TRM)
- VREF Status and Control Register (VREF_SC)
- Voltage Reference Enabled, SC[VREFEN] = 1
- Internal voltage regulator
- MCG Control Register 1 (MCG_C1)
- MCG Control Register 2 (MCG_C2)
- MCG Status Register (MCG_S)
- MCG Miscellaneous Control Register (MCG_MC)
- LIRC divider 1
- MCG-Lite in Low-power mode
- Chip-specific OSC information
- OSC Signal Descriptions
- External Clock Connections
- OSC Memory Map/Register Definition
- OSC module modes
- Counter
- Low power modes operation
- Chip-specific TPM information
- TPM instantiation information
- Trigger options
- TPM Signal Descriptions
- TPM_EXTCLK — TPM External Clock
- Status and Control (TPMx_SC)
- Counter (TPMx_CNT)
- Modulo (TPMx_MOD)
- Channel (n) Status and Control (TPMx_CnSC)
- Channel (n) Value (TPMx_CnV)
- Channel Polarity (TPMx_POL)
- Configuration (TPMx_CONF)
- Prescaler
- Input Capture Mode
- Output Compare Mode
- Edge-Aligned PWM (EPWM) Mode
- Center-Aligned PWM (CPWM) Mode
- Registers Updated from Write Buffers
- Output triggers
- Reset Overview
- Chip-specific PIT information
- PIT/DAC triggers
- PIT Module Control Register (PIT_MCR)
- PIT Upper Lifetime Timer Register (PIT_LTMR64H)
- Timer Load Value Register (PIT_LDVALn)
- Timer Control Register (PIT_TCTRLn)
- Timer Flag Register (PIT_TFLGn)
- Interrupts
- Example configuration for chained timers
- Example configuration for the lifetime timer
- Chip-specific LPTMR information
- LPTMR prescaler/glitch filter clocking options
- Low Power Timer Prescale Register (LPTMRx_PSR)
- Low Power Timer Compare Register (LPTMRx_CMR)
- LPTMR prescaler/glitch filter
- LPTMR compare
- LPTMR hardware trigger
- Chip-specific RTC information
- RTC Time Seconds Register (RTC_TSR)
- RTC Time Alarm Register (RTC_TAR)
- RTC Control Register (RTC_CR)
- RTC Status Register (RTC_SR)
- RTC Lock Register (RTC_LR)
- RTC Interrupt Enable Register (RTC_IER)
- Time counter
- Time alarm
- Update mode
- Chip-specific USBFS information
- USB Power Distribution
- USB power management
- USBFS Features
- On-chip transceiver required external components
- Programmers interface
- USB data transfers—Receive (Rx) and Transmit (Tx)
- Addressing BDT entries
- USB transaction
- Peripheral ID register (USBx_PERID)
- Peripheral Revision register (USBx_REV)
- Interrupt Status register (USBx_ISTAT)
- Interrupt Enable register (USBx_INTEN)
- Error Interrupt Status register (USBx_ERRSTAT)
- Error Interrupt Enable register (USBx_ERREN)
- Status register (USBx_STAT)
- Control register (USBx_CTL)
- Address register (USBx_ADDR)
- Frame Number register Low (USBx_FRMNUML)
- BDT Page Register 2 (USBx_BDTPAGE2)
- Endpoint Control register (USBx_ENDPTn)
- USB Control register (USBx_USBCTRL)
- USB OTG Control register (USBx_CONTROL)
- USB Transceiver Control register 0 (USBx_USBTRC0)
- Frame Adjust Register (USBx_USBFRMADJUST)
- IRC48M oscillator enable register (USBx_CLK_RECOVER_IRC_EN)
- Clock recovery combined interrupt enable (USBx_CLK_RECOVER_INT_EN)
- Clock recovery separated interrupt status (USBx_CLK_RECOVER_INT_STATUS)
- Chip-specific SPI information
- SPSCK — SPI Serial Clock
- SPI Baud Rate Register (SPIx_BR)
- SPI Control Register 2 (SPIx_C2)
- SPI Control Register 1 (SPIx_C1)
- SPI Match Register low (SPIx_ML)
- SPI match register high (SPIx_MH)
- SPI data register high (SPIx_DH)
- SPI clear interrupt register (SPIx_CI)
- SPI control register 3 (SPIx_C3)
- Slave mode
- SPI FIFO Mode
- SPI Transmission by DMA
- Data Transmission Length
- SPI clock formats
- SPI baud rate generation
- Error conditions
- Low-power mode options
- Reset
- Pseudo-Code Example
- Chip-specific I2C information
- I2C Address Register 1 (I2Cx_A1)
- I2C Control Register 1 (I2Cx_C1)
- I2C Status register (I2Cx_S)
- I2C Data I/O register (I2Cx_D)
- I2C Programmable Input Glitch Filter Register (I2Cx_FLT)
- I2C Range Address register (I2Cx_RA)
- I2C Address Register 2 (I2Cx_A2)
- I2C SCL Low Timeout Register Low (I2Cx_SLTL)
- Address matching
- System management bus specification
- Resets
- Programmable input glitch filter
- DMA support
- Double buffering mode
- Chip-specific LPUART information
- Signal Descriptions
- Register definition
- LPUART Baud Rate Register (LPUARTx_BAUD)
- LPUART Status Register (LPUARTx_STAT)
- LPUART Control Register (LPUARTx_CTRL)
- LPUART Data Register (LPUARTx_DATA)
- LPUART Match Address Register (LPUARTx_MATCH)
- Transmitter functional description
- Receiver functional description
- Additional LPUART functions
- Interrupts and status flags
- Chip-specific UART information
- UART signal descriptions
- UART Baud Rate Registers: High (UARTx_BDH)
- UART Baud Rate Registers: Low (UARTx_BDL)
- UART Control Register 2 (UARTx_C2)
- UART Status Register 1 (UARTx_S1)
- UART Status Register 2 (UARTx_S2)
- UART Control Register 3 (UARTx_C3)
- UART Data Register (UARTx_D)
- UART Match Address Registers 1 (UARTx_MA1)
- UART Match Address Registers 2 (UARTx_MA2)
- UART Control Register 5 (UARTx_C5)
- UART 7816 Control Register (UARTx_C7816)
- UART 7816 Interrupt Enable Register (UARTx_IE7816)
- UART 7816 Interrupt Status Register (UARTx_IS7816)
- UART 7816 Wait Parameter Register (UARTx_WP7816)
- UART 7816 Wait FD Register (UARTx_WF7816)
- UART 7816 Transmit Length Register (UARTx_TL7816)
- UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0)
- UART 7816 Wait Parameter Register A (UARTx_WP7816A_T0)
- UART 7816 Wait Parameter Register B (UARTx_WP7816B_T0)
- UART 7816 Wait and Guard Parameter Register (UARTx_WGP7816_T1)
- Receiver
- Baud rate generation
- Data format (non ISO-7816)
- Single-wire operation
- ISO-7816/smartcard support
- RXEDGIF description
- Initialization sequence (non ISO-7816)
- Overrun (OR) flag implications
- Match address registers
- Chip-specific FlexIO information
- Version ID Register (FLEXIO_VERID)
- Parameter Register (FLEXIO_PARAM)
- FlexIO Control Register (FLEXIO_CTRL)
- Shifter Status Register (FLEXIO_SHIFTSTAT)
- Shifter Error Register (FLEXIO_SHIFTERR)
- Shifter Status Interrupt Enable (FLEXIO_SHIFTSIEN)
- Shifter Error Interrupt Enable (FLEXIO_SHIFTEIEN)
- Shifter Status DMA Enable (FLEXIO_SHIFTSDEN)
- Shifter Configuration N Register (FLEXIO_SHIFTCFGn)
- Shifter Buffer N Register (FLEXIO_SHIFTBUFn)
- Shifter Buffer N Bit Swapped Register (FLEXIO_SHIFTBUFBISn)
- Shifter Buffer N Bit Byte Swapped Register (FLEXIO_SHIFTBUFBBSn)
- Timer Configuration N Register (FLEXIO_TIMCFGn)
- Timer Compare N Register (FLEXIO_TIMCMPn)
- Timer operation
- Pin operation
- UART Receive
- SPI Master
- SPI Slave
- I2C Master
- I2S Master
- I2S Slave
- Chip-specific I2S information
- External signals
- SAI Transmit Control Register (I2Sx_TCSR)
- SAI Transmit Configuration 2 Register (I2Sx_TCR2)
- SAI Transmit Configuration 3 Register (I2Sx_TCR3)
- SAI Transmit Configuration 4 Register (I2Sx_TCR4)
- SAI Transmit Configuration 5 Register (I2Sx_TCR5)
- SAI Transmit Data Register (I2Sx_TDRn)
- SAI Receive Control Register (I2Sx_RCSR)
- SAI Receive Configuration 2 Register (I2Sx_RCR2)
- SAI Receive Configuration 3 Register (I2Sx_RCR3)
- SAI Receive Configuration 4 Register (I2Sx_RCR4)
- SAI Receive Configuration 5 Register (I2Sx_RCR5)
- SAI Receive Mask Register (I2Sx_RMR)
- SAI MCLK Control Register (I2Sx_MCR)
- SAI resets
- Synchronous modes
- Data FIFO
- Word mask register
- Chip-specific GPIO information
- GPIO signal descriptions
- Port Data Output Register (GPIOx_PDOR)
- Port Set Output Register (GPIOx_PSOR)
- Port Toggle Output Register (GPIOx_PTOR)
- Port Data Direction Register (GPIOx_PDDR)
- BME decorated stores
- BME decorated loads
- Additional details on decorated addresses and GPIO accesses
- MTB_DWT Memory Map
- System ROM Memory Map
- Glossary
- Flash Configuration Field Description
- Register Descriptions
- Flash Operation in Low-Power Modes
- Read While Write (RWW)
- Margin Read Commands
- Flash Command Description
- Security
- Reset Sequence
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