SPIx_CI field descriptions (continued)Field Description0 Transmit FIFO overflow condition has not occurred1 Transmit FIFO overflow condition occurred4RXFOFReceive FIFO overflow flagThis flag indicates that a receive FIFO overflow condition has occurred.0 Receive FIFO overflow condition has not occurred1 Receive FIFO overflow condition occurred3TNEAREFCITransmit FIFO nearly empty flag clear interruptWriting 1 to this bit clears the TNEAREF interrupt provided that C3[3] is set.2RNFULLFCIReceive FIFO nearly full flag clear interruptWriting 1 to this bit clears the RNFULLF interrupt provided that C3[3] is set.1SPTEFCITransmit FIFO empty flag clear interruptWriting 1 to this bit clears the SPTEF interrupt provided that C3[3] is set.0SPRFCIReceive FIFO full flag clear interruptWriting 1 to this bit clears the SPRF interrupt provided that C3[3] is set.35.4.10 SPI control register 3 (SPIx_C3)This register introduces a 64-bit FIFO function on both transmit and receive buffers. Itapplies only for an instance of the SPI module that supports the FIFO feature.FIFO mode is enabled by setting the FIFOMODE bit to 1. A write to this register occursonly when it sets the FIFOMODE bit to 1.Using this FIFO feature allows the SPI to provide high speed transfers of large amountsof data without consuming large amounts of the CPU bandwidth.Enabling this FIFO function affects the behavior of some of the read/write buffer flags inthe S register as follows:• When the receive FIFO has data in it, S[RFIFOEF] is 0. As a result:• If C2[RXDMAE] is 1, RFIFOEF_b generates a receive DMA request. The DMArequest remains active until RFIFOEF is set to 1, indicating the receive buffer isempty.• If C2[RXDMAE] is 0 and C1[SPIE] is 1, SPRF interrupts the CPU.• When the transmit FIFO is not full, S[TXFULLF] is 0. As a result:• If C2[TXDMAE] is 1, TXFULLF_b generates a transmit DMA request. TheDMA request remains active until TXFULLF is set to 1, indicating the transmitFIFO is full.• If C2[TXDMAE] is 0 and C1[SPTIE] is 1, SPTEF interrupts the CPU.Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016586 Freescale Semiconductor, Inc.
