GPIOx_PCOR field descriptions (continued)Field DescriptionWriting to this register will update the contents of the corresponding bit in the Port Data Output Register(PDOR) as follows:0 Corresponding bit in PDORn does not change.1 Corresponding bit in PDORn is cleared to logic 0.41.3.4 Port Toggle Output Register (GPIOx_PTOR)Address: Base address + Ch offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0W PTTOReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0GPIOx_PTOR field descriptionsField DescriptionPTTO Port Toggle OutputWriting to this register will update the contents of the corresponding bit in the PDOR as follows:0 Corresponding bit in PDORn does not change.1 Corresponding bit in PDORn is set to the inverse of its existing logic state.41.3.5 Port Data Input Register (GPIOx_PDIR)NOTEDo not modify pin configuration registers associated with pinsnot available in your selected package. All unbonded pins notavailable in your package will default to DISABLE state forlowest power consumption.Address: Base address + 10h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R PDIWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 41 General-Purpose Input/Output (GPIO)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 827
