SPIx_S field descriptions (continued)Field DescriptionWhen FIFOMODE and DMA are both enabled, the inverted RXIFOEF is used to trigger a DMA transfer.So when the receive FIFO is not empty, the DMA request is active, and remains active until the FIFO isempty.NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) registerand both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If thistype of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If thistype of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.0 Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode willempty the read FIFO.1 Read FIFO is empty.35.4.2 SPI Baud Rate Register (SPIx_BR)Use this register to set the prescaler and bit rate divisor for an SPI master. This registermay be read or written at any time.Address: Base address + 1h offsetBit 7 6 5 4 3 2 1 0Read 0 SPPR[2:0] SPR[3:0]WriteReset 0 0 0 0 0 0 0 0SPIx_BR field descriptionsField Description7ReservedThis field is reserved.This read-only field is reserved and always has the value 0.6–4SPPR[2:0]SPI Baud Rate Prescale DivisorThis 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler isthe SPI module clock. The output of this prescaler drives the input of the SPI baud rate divider. Refer tothe description of “SPI Baud Rate Generation” for details.000 Baud rate prescaler divisor is 1.001 Baud rate prescaler divisor is 2.010 Baud rate prescaler divisor is 3.011 Baud rate prescaler divisor is 4.100 Baud rate prescaler divisor is 5.101 Baud rate prescaler divisor is 6.110 Baud rate prescaler divisor is 7.111 Baud rate prescaler divisor is 8.SPR[3:0] SPI Baud Rate DivisorTable continues on the next page...Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016578 Freescale Semiconductor, Inc.
