In 16-bit mode, reading either byte (the MH or ML register) latches the contents of bothbytes into a buffer where they remain latched until the other byte is read. Writing toeither byte (the MH or ML register) latches the value into a buffer. When both bytes havebeen written, they are transferred as a coherent value into the SPI match registers.Address: Base address + 4h offsetBit 7 6 5 4 3 2 1 0Read Bits[7:0]WriteReset 0 0 0 0 0 0 0 0SPIx_ML field descriptionsField DescriptionBits[7:0] Hardware compare value (low byte)35.4.6 SPI match register high (SPIx_MH)Refer to the description of the ML register.Address: Base address + 5h offsetBit 7 6 5 4 3 2 1 0Read Bits[15:8]WriteReset 0 0 0 0 0 0 0 0SPIx_MH field descriptionsField DescriptionBits[15:8] Hardware compare value (high byte)35.4.7 SPI Data Register low (SPIx_DL)This register, together with the DH register, is both the input and output register for SPIdata. A write to the registers writes to the transmit data buffer, allowing data to be queuedand transmitted.When the SPI is configured as a master, data queued in the transmit data buffer istransmitted immediately after the previous transmission has completed.The SPTEF bit in the S register indicates when the transmit data buffer is ready to acceptnew data. When the transmit DMA request is disabled (TXDMAE is 0): The S registermust be read when S[SPTEF] is set before writing to the SPI data registers; otherwise, theChapter 35 Serial Peripheral Interface (SPI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 583
