For more information regarding the calibration procedure, please refer to the Calibrationfunction section.Address: 4003_B000h base + 30h offset = 4003_B030hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 MGWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0ADCx_MG field descriptionsField Description31–16ReservedThis field is reserved.This read-only field is reserved and always has the value 0.MG Minus-Side Gain23.4.11 ADC Plus-Side General Calibration Value Register(ADCx_CLPD)The Plus-Side General Calibration Value Registers (CLPx) contain calibrationinformation that is generated by the calibration function. These registers contain sevencalibration values of varying widths: CLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0],CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the self-calibration sequence is done, that is, CAL is cleared. If these registers are written by theuser after calibration, the linearity error specifications may not be met.For more information regarding the calibration procedure, please refer to the Calibrationfunction section.Address: 4003_B000h base + 34h offset = 4003_B034hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 CLPDWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0ADCx_CLPD field descriptionsField Description31–6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.CLPD Calibration ValueCalibration ValueMemory map and register definitionsKL27 Sub-Family Reference Manual , Rev. 5, 01/2016356 Freescale Semiconductor, Inc.
