NXP Semiconductors MKL27Z128VFM4 Reference Manual

Contents

Section number Title Page11.6 Detailed signal description............................................................................................................................................12911.7 Memory map and register definition.............................................................................................................................12911.7.1 Pin Control Register n (PORTx_PCRn).........................................................................................................13511.7.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................... 13811.7.3 Global Pin Control High Register (PORTx_GPCHR)................................................................................... 13811.7.4 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 13911.8 Functional description...................................................................................................................................................13911.8.1 Pin control...................................................................................................................................................... 13911.8.2 Global pin control.......................................................................................................................................... 14011.8.3 External interrupts..........................................................................................................................................140Chapter 12System Integration Module (SIM)12.1 Chip-specific SIM information..................................................................................................................................... 14312.1.1 COP clocks.....................................................................................................................................................14312.2 Introduction...................................................................................................................................................................14312.2.1 Features.......................................................................................................................................................... 14312.3 Memory map and register definition.............................................................................................................................14412.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 14512.3.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................14612.3.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 14812.3.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 15012.3.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 15112.3.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 15312.3.7 System Device Identification Register (SIM_SDID).....................................................................................15412.3.8 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................15612.3.9 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................15812.3.10 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................16012.3.11 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................16212.3.12 System Clock Divider Register 1 (SIM_CLKDIV1)..................................................................................... 162KL27 Sub-Family Reference Manual , Rev. 5, 01/20168 Freescale Semiconductor, Inc.