39.3.3 FlexIO Control Register (FLEXIO_CTRL).Address: 4005_F000h base + 8h offset = 4005_F008hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RDOZENDBGE 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0FASTACCSWRSTFLEXENWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FLEXIO_CTRL field descriptionsField Description31DOZENDoze EnableDisables FlexIO operation in Doze modes. This field is ignored and the FlexIO always disabled in low-leakage stop modes.0 FlexIO enabled in Doze modes.1 FlexIO disabled in Doze modes.30DBGEDebug EnableEnables FlexIO operation in Debug mode.0 FlexIO is disabled in debug modes.1 FlexIO is enabled in debug modes29–3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.2FASTACCFast AccessEnables fast register accesses to FlexIO registers, but requires the FlexIO clock to be at least twice thefrequency of the bus clock.0 Configures for normal register accesses to FlexIO1 Configures for fast register accesses to FlexIO1SWRSTSoftware ResetThe FlexIO Control Register is not affected by the software reset, all other logic in the FlexIO is affected bythe software reset and register accesses are ignored until this bit is cleared. This register bit will remainset until cleared by software, and the reset has cleared in the FlexIO clock domain.Table continues on the next page...Memory Map and RegistersKL27 Sub-Family Reference Manual , Rev. 5, 01/2016752 Freescale Semiconductor, Inc.
