FLEXIO memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4005_F38C Shifter Buffer N Bit Byte Swapped Register(FLEXIO_SHIFTBUFBBS3) 32 R/W 0000_0000h 39.3.16/7624005_F400 Timer Control N Register (FLEXIO_TIMCTL0) 32 R/W 0000_0000h 39.3.17/7624005_F404 Timer Control N Register (FLEXIO_TIMCTL1) 32 R/W 0000_0000h 39.3.17/7624005_F408 Timer Control N Register (FLEXIO_TIMCTL2) 32 R/W 0000_0000h 39.3.17/7624005_F40C Timer Control N Register (FLEXIO_TIMCTL3) 32 R/W 0000_0000h 39.3.17/7624005_F480 Timer Configuration N Register (FLEXIO_TIMCFG0) 32 R/W 0000_0000h 39.3.18/7644005_F484 Timer Configuration N Register (FLEXIO_TIMCFG1) 32 R/W 0000_0000h 39.3.18/7644005_F488 Timer Configuration N Register (FLEXIO_TIMCFG2) 32 R/W 0000_0000h 39.3.18/7644005_F48C Timer Configuration N Register (FLEXIO_TIMCFG3) 32 R/W 0000_0000h 39.3.18/7644005_F500 Timer Compare N Register (FLEXIO_TIMCMP0) 32 R/W 0000_0000h 39.3.19/7664005_F504 Timer Compare N Register (FLEXIO_TIMCMP1) 32 R/W 0000_0000h 39.3.19/7664005_F508 Timer Compare N Register (FLEXIO_TIMCMP2) 32 R/W 0000_0000h 39.3.19/7664005_F50C Timer Compare N Register (FLEXIO_TIMCMP3) 32 R/W 0000_0000h 39.3.19/76639.3.1 Version ID Register (FLEXIO_VERID).Address: 4005_F000h base + 0h offset = 4005_F000hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R MAJOR MINOR FEATUREWReset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FLEXIO_VERID field descriptionsField Description31–24MAJORMajor Version NumberTable continues on the next page...Memory Map and RegistersKL27 Sub-Family Reference Manual , Rev. 5, 01/2016750 Freescale Semiconductor, Inc.
