received, it is possible that the application code will read the data buffer such thatsufficient room will be made to store the dataword that is being NACKed. Even if roomhas been made in the data buffer after the transmission of a NACK is completed, thereceived data will always be discarded as a result of an overflow and theET7816[RXTHRESHOLD] value will be incremented by one. However, if sufficientspace now exists to write the received data which was NACK'ed, S1[OR] will be blockedand kept from asserting.38.9.5 Match address registersThe two match address registers allow a second match address function for a broadcast orgeneral call address to the serial bus, as an example.38.9.6 Clearing 7816 wait timer (WT, BWT, CWT) interruptsThe 7816 wait timer interrupts associated with IS7816[WT], IS7816[BWT], andIS7816[CWT] will automatically reassert if they are cleared and the wait time is stillviolated. This behavior is similar to most of the other interrupts on the UART. In mostcases, if the condition that caused the interrupt to trigger still exists when the interrupt iscleared, then the interrupt will reassert. For example, consider the following scenario:1. IS7816[WT] is programmed to assert after 9600 cycles of unresponsiveness.2. The 9600 cycles pass without a response resulting in the WT interrupt asserting.3. The IS7816[WT] is cleared at cycle 9700 by the interrupt service routine.4. After the WT interrupt has been cleared, the smartcard remains unresponsive. Atcycle 9701 the WT interrupt will be reasserted.If the intent of clearing the interrupt is such that it does not reassert, the interrupt serviceroutine must remove or clear the condition that originally caused the interrupt to assertprior to clearing the interrupt. There are multiple ways that this can be accomplished,including ensuring that an event that results in the wait timer resetting occurs, such as, thetransmission of another packet.38.9.7 Legacy and reverse compatibility considerationsRecent versions of the UART have added several new features. Whenever reasonablypossible, reverse compatibility was maintained. However, in some cases this was eithernot feasible or the behavior was deemed as not intended. This section describes severaldifferences to legacy operation that resulted from these recent enhancements. IfApplication informationKL27 Sub-Family Reference Manual , Rev. 5, 01/2016742 Freescale Semiconductor, Inc.
