12.3.6 System Options Register 7 (SIM_SOPT7)Address: 4004_7000h base + 1018h offset = 4004_8018hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0ADC0ALTTRGEN0ADC0PRETRGSEL ADC0TRGSELWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIM_SOPT7 field descriptionsField Description31–8ReservedThis field is reserved.This read-only field is reserved and always has the value 0.7ADC0ALTTRGENADC0 Alternate Trigger EnableEnables alternative conversion triggers for ADC0.0 ADC ADHWT trigger comes from TPM1 channel 0 and channel1.Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate anADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register.Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate anADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register.1 ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosingthe ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion.6–5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4ADC0PRETRGSELADC0 Pretrigger SelectSelects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN.NOTE: The ADC0PRETRGSEL function is ignored if ADC0ALTTRGEN = 0.0 Pre-trigger ADHWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADCconversion and store the result in ADC0_RA register.1 Pre-trigger ADHWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADCconversion and store the result in ADC0_RB register.Table continues on the next page...Chapter 12 System Integration Module (SIM)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 153
