Address: 4007_F000h base + 1h offset = 4007_F001hBit 7 6 5 4 3 2 1 0Read 0 0 SACKERR 0 MDM_AP SW LOCKUP 0WriteReset 0 0 0 0 0 0 0 0RCM_SRS1 field descriptionsField Description7ReservedThis field is reserved.This read-only field is reserved and always has the value 0.6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.5SACKERRStop Mode Acknowledge Error ResetIndicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or moreperipherals to acknowledge within approximately one second to enter stop mode.0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode4ReservedThis field is reserved.This read-only field is reserved and always has the value 0.3MDM_APMDM-AP System Reset RequestIndicates a reset has been caused by the host debugger system setting of the System Reset Request bitin the MDM-AP Control Register.0 Reset not caused by host debugger system setting of the System Reset Request bit1 Reset caused by host debugger system setting of the System Reset Request bit2SWSoftwareIndicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt andReset Control Register in the ARM core.0 Reset not caused by software setting of SYSRESETREQ bit1 Reset caused by software setting of SYSRESETREQ bit1LOCKUPCore LockupIndicates a reset has been caused by the ARM core indication of a LOCKUP event.0 Reset not caused by core LOCKUP event1 Reset caused by core LOCKUP event0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.22.2.3 Reset Pin Filter Control register (RCM_RPFC)NOTEThe reset values of bits 2-0 are for Chip POR only. They areunaffected by other reset types.Reset memory map and register descriptionsKL27 Sub-Family Reference Manual , Rev. 5, 01/2016328 Freescale Semiconductor, Inc.
