DAC memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4003_F000 DAC Data Low Register (DAC0_DAT0L) 8 R/W 00h 25.4.1/4154003_F001 DAC Data High Register (DAC0_DAT0H) 8 R/W 00h 25.4.2/4154003_F002 DAC Data Low Register (DAC0_DAT1L) 8 R/W 00h 25.4.1/4154003_F003 DAC Data High Register (DAC0_DAT1H) 8 R/W 00h 25.4.2/4154003_F020 DAC Status Register (DAC0_SR) 8 R/W See section 25.4.3/4164003_F021 DAC Control Register (DAC0_C0) 8 R/W 00h 25.4.4/4174003_F022 DAC Control Register 1 (DAC0_C1) 8 R/W 00h 25.4.5/4184003_F023 DAC Control Register 2 (DAC0_C2) 8 R/W 01h 25.4.6/41825.4.1 DAC Data Low Register (DACx_DATnL)Address: 4003_F000h base + 0h offset + (2d × i), where i=0d to 1dBit 7 6 5 4 3 2 1 0Read DATA0WriteReset 0 0 0 0 0 0 0 0DACx_DATnL field descriptionsField DescriptionDATA0 DATA0When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the followingformula: V out = V in * (1 + DACDAT0[11:0])/4096When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.25.4.2 DAC Data High Register (DACx_DATnH)Address: 4003_F000h base + 1h offset + (2d × i), where i=0d to 1dBit 7 6 5 4 3 2 1 0Read 0 DATA1WriteReset 0 0 0 0 0 0 0 0DACx_DATnH field descriptionsField Description7–4ReservedThis field is reserved.This read-only field is reserved and always has the value 0.DATA1 DATA1Table continues on the next page...Chapter 25 12-bit Digital-to-Analog Converter (DAC)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 415
