12.3.11 System Clock Gating Control Register 7 (SIM_SCGC7)Address: 4004_7000h base + 1040h offset = 4004_8040hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 DMA 0WReset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0SIM_SCGC7 field descriptionsField Description31–9ReservedThis field is reserved.This read-only field is reserved and always has the value 0.8DMADMA Clock Gate ControlControls the clock gate to the DMA module.0 Clock disabled1 Clock enabledReserved This field is reserved.This read-only field is reserved and always has the value 0.12.3.12 System Clock Divider Register 1 (SIM_CLKDIV1)NOTEThe CLKDIV1 register cannot be written to when the device isin VLPR mode.NOTEReset value loaded during System Reset fromFTFA_FOPT[LPBOOT] (See Table 6-2).Address: 4004_7000h base + 1044h offset = 4004_8044hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R OUTDIV1 0 OUTDIV4 0WReset * * * * 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* Notes:OUTDIV1 field: The reset value depends on the FTFA_FOPT[LPBOOT]. It is loaded with 0000 (divide by 1), 0001 (divide by2), 0011 (divide by 4, or 0111 (divide by 8).•Memory map and register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016162 Freescale Semiconductor, Inc.
