CMPx_CR0 field descriptions (continued)Field DescriptionHYSTCTR Comparator hard block hysteresis controlDefines the programmable hysteresis level. The hysteresis values associated with each level are device-specific. See the Data Sheet of the device for the exact values.00 Level 001 Level 110 Level 211 Level 324.3.2 CMP Control Register 1 (CMPx_CR1)Address: 4007_3000h base + 1h offset = 4007_3001hBit 7 6 5 4 3 2 1 0Read SE WE TRIGM PMODE INV COS OPE ENWriteReset 0 0 0 0 0 0 0 0CMPx_CR1 field descriptionsField Description7SESample EnableSE must be clear to 0 and usage of sample operation is limited to a divided version of the bus clock.0 Sampling mode is not selected.1 Sampling mode is selected.6WEWindowing EnableThe CMP does not support window compare function and a 0 must always be written to WE.0 Windowing mode is not selected.1 Windowing mode is selected.5TRIGMTrigger Mode EnableCMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, theCMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled.CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DACin order to generate a triggered compare.Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resourcetrigger is received.See the chip configuration for details about the external timer resource.0 Trigger mode is disabled.1 Trigger mode is enabled.4PMODEPower Mode SelectTable continues on the next page...Memory map/register definitionsKL27 Sub-Family Reference Manual , Rev. 5, 01/2016398 Freescale Semiconductor, Inc.
