UARTx_C1 field descriptions (continued)Field DescriptionDetermines whether the UART generates and checks for even parity or odd parity. With even parity, aneven number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an oddnumber of 1s clears the parity bit and an even number of 1s sets the parity bit. This field must be clearedwhen C7816[ISO_7816E] is set/enabled.0 Even parity.1 Odd parity.38.4.4 UART Control Register 2 (UARTx_C2)This register can be read or written at any time.Address: 4006_C000h base + 3h offset = 4006_C003hBit 7 6 5 4 3 2 1 0Read TIE TCIE RIE ILIE TE RE RWU SBKWriteReset 0 0 0 0 0 0 0 0UARTx_C2 field descriptionsField Description7TIETransmitter Interrupt or DMA Transfer Enable.Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, based on the state ofC5[TDMAS].NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be writtenunless servicing a DMA request.0 TDRE interrupt and DMA transfer requests disabled.1 TDRE interrupt or DMA transfer requests enabled.6TCIETransmission Complete Interrupt EnableEnables the transmission complete flag, S1[TC], to generate interrupt requests .0 TC interrupt requests disabled.1 TC interrupt requests enabled.5RIEReceiver Full Interrupt or DMA Transfer EnableEnables S1[RDRF] to generate interrupt requests or DMA transfer requests, based on the state ofC5[RDMAS].0 RDRF interrupt and DMA transfer requests disabled.1 RDRF interrupt or DMA transfer requests enabled.4ILIEIdle Line Interrupt EnableEnables the idle line flag, S1[IDLE], to generate interrupt requestsTable continues on the next page...Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 685
