24.3.4 CMP Status and Control Register (CMPx_SCR)Address: 4007_3000h base + 3h offset = 4007_3003hBit 7 6 5 4 3 2 1 0Read 0 DMAEN 0 IER IEF CFR CFF COUTWrite w1c w1cReset 0 0 0 0 0 0 0 0CMPx_SCR field descriptionsField Description7ReservedThis field is reserved.This read-only field is reserved and always has the value 0.6DMAENDMA Enable ControlEnables the DMA transfer triggered from the CMP module. When this field is set, a DMA request isasserted when CFR or CFF is set.0 DMA is disabled.1 DMA is enabled.5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4IERComparator Interrupt Enable RisingEnables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR isset.0 Interrupt is disabled.1 Interrupt is enabled.3IEFComparator Interrupt Enable FallingEnables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF isset.0 Interrupt is disabled.1 Interrupt is enabled.2CFRAnalog Comparator Flag RisingDetects a rising-edge on COUT, when set, during normal operation. CFR is cleared by writing 1 to it.During Stop modes, CFR is edge sensitive .0 Rising-edge on COUT has not been detected.1 Rising-edge on COUT has occurred.1CFFAnalog Comparator Flag FallingDetects a falling-edge on COUT, when set, during normal operation. CFF is cleared by writing 1 to it.During Stop modes, CFF is edge sensitive .0 Falling-edge on COUT has not been detected.1 Falling-edge on COUT has occurred.Table continues on the next page...Memory map/register definitionsKL27 Sub-Family Reference Manual , Rev. 5, 01/2016400 Freescale Semiconductor, Inc.
