If (CnV = 0x0000) then the channel (n) output is a 0% duty cycle CPWM signal.If (CnV > MOD), then the channel (n) output is a 100% duty cycle CPWM signal,although the CHnF bit is set when the counter changes from incrementing todecrementing. Therefore, MOD must be less than 0xFFFF in order to get a 100% dutycycle CPWM signal.29.5.8 Registers Updated from Write Buffers29.5.8.1 MOD Register UpdateIf (CMOD[1:0] = 0:0) then MOD register is updated when MOD register is written.If (CMOD[1:0] ≠ 0:0), then MOD register is updated according to the CPWMS bit, thatis:• If the selected mode is not CPWM then MOD register is updated after MOD registerwas written and the TPM counter changes from MOD to zero.• If the selected mode is CPWM then MOD register is updated after MOD register waswritten and the TPM counter changes from MOD to (MOD – 1).29.5.8.2 CnV Register UpdateIf (CMOD[1:0] = 0:0) then CnV register is updated when CnV register is written.If (CMOD[1:0] ≠ 0:0), then CnV register is updated according to the selected mode, thatis:• If the selected mode is output compare then CnV register is updated on the next TPMcounter increment (end of the prescaler counting) after CnV register was written.• If the selected mode is EPWM then CnV register is updated after CnV register waswritten and the TPM counter changes from MOD to zero.• If the selected mode is CPWM then CnV register is updated after CnV register waswritten and the TPM counter changes from MOD to (MOD – 1).Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016484 Freescale Semiconductor, Inc.
