MCG memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4006_4000 MCG Control Register 1 (MCG_C1) 8 R/W 40h 27.2.1/4354006_4001 MCG Control Register 2 (MCG_C2) 8 R/W 01h 27.2.2/4364006_4006 MCG Status Register (MCG_S) 8 R 04h 27.2.3/4374006_4008 MCG Status and Control Register (MCG_SC) 8 R/W 00h 27.2.4/4374006_4018 MCG Miscellaneous Control Register (MCG_MC) 8 R/W 00h 27.2.5/43827.2.1 MCG Control Register 1 (MCG_C1)Address: 4006_4000h base + 0h offset = 4006_4000hBit 7 6 5 4 3 2 1 0Read CLKS 0 IRCLKEN IREFSTENWriteReset 0 1 0 0 0 0 0 0MCG_C1 field descriptionsField Description7–6CLKSClock Source SelectSelects the clock source for MCGOUTCLK.00 Selects HIRC clock as the main clock source. This is HIRC mode.01 Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M mode.10 Selects external clock as the main clock source. This is EXT mode.11 Reserved. Writing 11 takes no effect.5–2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1IRCLKENInternal Reference Clock EnableEnables the IRC source.0 LIRC is disabled.1 LIRC is enabled.0IREFSTENInternal Reference Stop EnableControls whether the IRC source remains enabled when the MCG_Lite enters Stop mode.0 LIRC is disabled in Stop mode.1 LIRC is enabled in Stop mode, if IRCLKEN is set.Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 435
