9.3.2 MDM-AP Status RegisterTable 9-4. MDM-AP Status register assignmentsBit Name Description0 Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset.The bit is also cleared at launch of a mass erase command due to write ofFlash Mass Erase in Progress bit in MDM AP Control Register. The FlashMass Erase Acknowledge is set after Flash control logic has started themass erase operation.When mass erase is disabled (via MEEN and SEC settings), an eraserequest due to setting of Flash Mass Erase in Progress bit is notacknowledged.1 Flash Ready Indicates Flash has been initialized and debugger can be configured evenif system is continuing to be held in reset via the debugger.2 System Security Indicates the security state. When secure, the debugger does not haveaccess to the system bus or any memory mapped peripherals. This bitindicates when the part is locked and no system bus access is possible.3 System Reset Indicates the system reset state.0 System is in reset.1 System is not in reset.4 Reserved5 Mass Erase Enable Indicates if the MCU can be mass erased or not0 Mass erase is disabled.1 Mass erase is enabled .6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled.0 Disabled1 Enabled7 LP Enabled Decode of SMC_PMCTRL[STOPM] field to indicate that VLPS, LLS, orVLLSx are the selected power mode the next time the ARM Core entersDeep Sleep.0 Low Power Stop Mode is not enabled.1 Low Power Stop Mode is enabled.Usage intended for debug operation in which Run to VLPS is attempted.Per debug definition, the system actually enters the Stop state. Adebugger should interpret deep sleep indication (with SLEEPDEEP andSLEEPING asserted), in conjunction with this bit asserted as thedebugger-VLPS status indication.8 Very Low Power Mode Indicates current power mode is VLPx. This bit is not ‘sticky’ and shouldalways represent whether VLPx is enabled or not.This bit is used to throttle SWD_CLK frequency up/down.9 LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger willlose communication while the system is in LLS (including access to thisregister). Once communication is reestablished, this bit indicates that thesystem had been in LLS. Since the debug modules held their state duringLLS, they do not need to be reconfigured.Table continues on the next page...Chapter 9 DebugKL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 107
