AIPS_MPRA field descriptions (continued)Field Description0 This master is not trusted for write accesses.1 This master is trusted for write accesses.20MPL2Master 2 Privilege LevelSpecifies how the privilege level of the master is determined.0 Accesses from this master are forced to user-mode.1 Accesses from this master are not forced to user-mode.19ReservedThis field is reserved.This read-only field is reserved and always has the value 0.18MTR3Master 3 Trusted For ReadDetermines whether the master is trusted for read accesses.0 This master is not trusted for read accesses.1 This master is trusted for read accesses.17MTW3Master 3 Trusted For WritesDetermines whether the master is trusted for write accesses.0 This master is not trusted for write accesses.1 This master is trusted for write accesses.16MPL3Master 3 Privilege LevelSpecifies how the privilege level of the master is determined.0 Accesses from this master are forced to user-mode.1 Accesses from this master are not forced to user-mode.19.3.2 Peripheral Access Control Register (AIPS_PACRn)The following table shows the location of each peripheral slot's PACR field in the PACRregisters.Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0]0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR70x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR150x28 PACRC PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR230x2C PACRD PACR24 PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31Address: 0h base + 20h offset + (4d × i), where i=0d to 3dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0 SP0 WP0 TP0 0 SP1 WP1 TP1 0 SP2 WP2 TP2 0 SP3 WP3 TP3WReset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016286 Freescale Semiconductor, Inc.
