The crossbar switch connects bus masters and bus slaves using a crossbar switchstructure. This structure allows up to four bus masters to access different bus slavessimultaneously, while providing arbitration among the bus masters when they access thesame slave.17.2.1 FeaturesThe crossbar switch includes these features:• Symmetric crossbar bus switch implementation• Allows concurrent accesses from different masters to different slaves• Up to single-clock 32-bit transfer• Programmable configuration for fixed-priority or round-robin slave port arbitration(see the chip-specific information).17.3 Memory Map / Register DefinitionThis crossbar switch is designed for minimal gate count. It, therefore, has no memory-mapped configuration registers.Please see the chip-specific information for information on whether the arbitrationmethod in the crossbar switch is programmable, and by which module.17.4 Functional Description17.4.1 General operationWhen a master accesses the crossbar switch, the access is immediately taken. If thetargeted slave port of the access is available, then the access is immediately presented onthe slave port. Single-clock or zero-wait-state accesses are possible through the crossbar.If the targeted slave port of the access is busy or parked on a different master port, therequesting master simply sees wait states inserted until the targeted slave port can servicethe master's request. The latency in servicing the request depends on each master'spriority level and the responding slave's access time.Memory Map / Register DefinitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016258 Freescale Semiconductor, Inc.
