35.4.4 SPI Control Register 1 (SPIx_C1)This read/write register includes the SPI enable control, interrupt enables, andconfiguration options.Address: Base address + 3h offsetBit 7 6 5 4 3 2 1 0Read SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFEWriteReset 0 0 0 0 0 1 0 0SPIx_C1 field descriptionsField Description7SPIESPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO(when FIFO is supported and enabled)When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): Enables the interruptfor SPI receive buffer full (SPRF) and mode fault (MODF) events.When the FIFO is supported and enabled (FIFOMODE is 1): This bit enables the SPI to interrupt the CPUwhen the receive FIFO is full. An interrupt occurs when the SPRF bit is set or the MODF bit is set.0 Interrupts from SPRF and MODF are inhibited—use polling (when FIFOMODE is not present or is 0)or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)1 Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) orRead FIFO Full Interrupts are enabled (when FIFOMODE is 1)6SPESPI System EnableEnables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, theSPI is disabled and forced into an idle state, and all status bits in the S register are reset.0 SPI system inactive1 SPI system enabled5SPTIESPI Transmit Interrupt EnableWhen the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This is the interruptenable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit buffer isempty (SPTEF is set).When the FIFO is supported and enabled (FIFOMODE is 1): This is the interrupt enable bit for SPItransmit FIFO empty (SPTEF). An interrupt occurs when the SPI transmit FIFO is empty (SPTEF is set).0 Interrupts from SPTEF inhibited (use polling)1 When SPTEF is 1, hardware interrupt requested4MSTRMaster/Slave Mode SelectSelects master or slave mode operation.0 SPI module configured as a slave SPI device1 SPI module configured as a master SPI deviceTable continues on the next page...Chapter 35 Serial Peripheral Interface (SPI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 581
