36.4.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)Address: Base address + Bh offsetBit 7 6 5 4 3 2 1 0Read SSLT[7:0]WriteReset 0 0 0 0 0 0 0 0I2Cx_SLTL field descriptionsField DescriptionSSLT[7:0] SSLT[7:0]Least significant byte of SCL low timeout value that determines the timeout period of SCL low.36.4.13 I2C Status register 2 (I2Cx_S2)Address: Base address + Ch offsetBit 7 6 5 4 3 2 1 0Read 0 0 0 0 0 0 ERROR EMPTYWrite w1cReset 0 0 0 0 0 0 0 1I2Cx_S2 field descriptionsField Description7ReservedThis field is reserved.This read-only field is reserved and always has the value 0.6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4ReservedThis field is reserved.This read-only field is reserved and always has the value 0.3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1ERRORError flagIndicates if there are read or write errors with the Tx and Rx buffers.0 The buffer is not full and all write/read operations have no errors.1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not setand the buffer is busy).Table continues on the next page...Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016626 Freescale Semiconductor, Inc.
