I2Cx_S field descriptions (continued)Field Description0 Acknowledge signal was received after the completion of one byte of data transmission on the bus1 No acknowledge signal detected36.4.5 I2C Data I/O register (I2Cx_D)Address: Base address + 4h offsetBit 7 6 5 4 3 2 1 0Read DATAWriteReset 0 0 0 0 0 0 0 0I2Cx_D field descriptionsField DescriptionDATA DataIn master transmit mode, when data is written to this register, a data transfer is initiated. The mostsignificant bit is sent first. In master receive mode, reading this register initiates receiving of the next byteof data.NOTE: When making the transition out of master receive mode, switch the I2C mode before reading theData register to prevent an inadvertent initiation of a master receive data transfer.In slave mode, the same functions are available after an address match occurs.The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for thetransmission to begin. For example, if the I2C module is configured for master transmit but a masterreceive is desired, reading the Data register does not initiate the receive.Reading the Data register returns the last byte received while the I2C module is configured in masterreceive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2Cbus, and neither can software verify that a byte has been written to the Data register correctly by reading itback.In master transmit mode, the first byte of data written to the Data register following assertion of MST (startbit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of thecalling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).36.4.6 I2C Control Register 2 (I2Cx_C2)Address: Base address + 5h offsetBit 7 6 5 4 3 2 1 0Read GCAEN ADEXT HDRS SBRC RMEN AD[10:8]WriteReset 0 0 0 0 0 0 0 0Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016620 Freescale Semiconductor, Inc.
