NXP Semiconductors MKL27Z128VFM4 Reference Manual Manual pdf 178 page image
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NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. Overview
  36. Typographic notation
  37. Module functional categories
  38. ARM Cortex-M0+ core modules
  39. Memories and memory interfaces
  40. Security and integrity modules
  41. Communication interfaces
  42. Human-machine interfaces
  43. Analog reference options
  44. ARM Cortex-M0+ core introduction
  45. Core privilege levels
  46. AWIC introduction
  47. Introduction
  48. Flash memory map
  49. FTFA_FOPT register
  50. SRAM retention in low power modes
  51. System memory map
  52. Bit Manipulation Engine
  53. Read-after-write sequence and required serialization of memory operations
  54. Clock definitions
  55. Device clock summary
  56. Internal clocking requirements
  57. Clock divider values after reset
  58. Clock gating
  59. PMC 1-kHz LPO clock
  60. RTC clocking
  61. LPTMR clocking
  62. TPM clocking
  63. LPUART clocking
  64. FlexIO clocking
  65. Power-on reset (POR)
  66. MCU resets
  67. RESET pin
  68. Boot sources
  69. Boot sequence
  70. DMA Wakeup
  71. Compute Operation
  72. Peripheral Doze
  73. Entering and exiting power modes
  74. Module operation in low-power modes
  75. Debug
  76. SWD status and control registers
  77. MDM-AP Control Register
  78. MDM-AP Status Register
  79. Debug resets
  80. Debug in low-power modes
  81. Debug and security
  82. KL27 Family Pinouts
  83. Module Signal Description Tables
  84. System modules
  85. Timer Modules
  86. Human-machine interfaces (HMI)
  87. Chip-specific PORT information
  88. Port control and interrupt summary
  89. Modes of operation
  90. External signal description
  91. Pin Control Register n (PORTx_PCRn)
  92. Global Pin Control Low Register (PORTx_GPCLR)
  93. Interrupt Status Flag Register (PORTx_ISFR)
  94. Global pin control
  95. Chip-specific SIM information
  96. Memory map and register definition
  97. System Options Register 1 (SIM_SOPT1)
  98. SOPT1 Configuration Register (SIM_SOPT1CFG)
  99. System Options Register 2 (SIM_SOPT2)
  100. System Options Register 4 (SIM_SOPT4)
  101. System Options Register 5 (SIM_SOPT5)
  102. System Options Register 7 (SIM_SOPT7)
  103. System Device Identification Register (SIM_SDID)
  104. System Clock Gating Control Register 4 (SIM_SCGC4)
  105. System Clock Gating Control Register 5 (SIM_SCGC5)
  106. System Clock Gating Control Register 6 (SIM_SCGC6)
  107. System Clock Gating Control Register 7 (SIM_SCGC7)
  108. Flash Configuration Register 1 (SIM_FCFG1)
  109. Flash Configuration Register 2 (SIM_FCFG2)
  110. Unique Identification Register Mid-High (SIM_UIDMH)
  111. Unique Identification Register Mid Low (SIM_UIDML)
  112. COP Control Register (SIM_COPC)
  113. Service COP (SIM_SRVCOP)
  114. COP watchdog operation
  115. Chip-Specific Information
  116. Functional Description
  117. The Kinetis Bootloader Configuration Area (BCA)
  118. Start-up Process
  119. Clock Configuration
  120. Bootloader Entry Point
  121. Bootloader Protocol
  122. Bootloader Packet Types
  123. Bootloader Command API
  124. Bootloader Exit state
  125. Peripherals Supported
  126. SPI Peripheral
  127. USB peripheral
  128. Get/SetProperty Command Properties
  129. Property Definitions
  130. Kinetis Bootloader Status Error Codes
  131. Bootloader errata
  132. Chip-specific SMC information
  133. Memory map and register descriptions
  134. Power Mode Protection register (SMC_PMPROT)
  135. Power Mode Control register (SMC_PMCTRL)
  136. Stop Control Register (SMC_STOPCTRL)
  137. Power Mode Status register (SMC_PMSTAT)
  138. Power mode entry/exit sequencing
  139. Run modes
  140. Wait modes
  141. Stop modes
  142. Debug in low power modes
  143. LVD reset operation
  144. I/O retention
  145. Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)
  146. Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)
  147. Regulator Status And Control register (PMC_REGSC)
  148. Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  149. Platform Control Register (MCM_PLACR)
  150. Compute Operation Control Register (MCM_CPO)
  151. Chip-specific AXBS-Lite information
  152. Features
  153. Arbitration
  154. Initialization/application information
  155. LLWU interrupt
  156. Block diagram
  157. LLWU signal descriptions
  158. LLWU Pin Enable 1 register (LLWU_PE1)
  159. LLWU Pin Enable 2 register (LLWU_PE2)
  160. LLWU Pin Enable 3 register (LLWU_PE3)
  161. LLWU Pin Enable 4 register (LLWU_PE4)
  162. LLWU Module Enable register (LLWU_ME)
  163. LLWU Flag 1 register (LLWU_F1)
  164. LLWU Flag 2 register (LLWU_F2)
  165. LLWU Flag 3 register (LLWU_F3)
  166. LLWU Pin Filter 1 register (LLWU_FILT1)
  167. LLWU Pin Filter 2 register (LLWU_FILT2)
  168. LLS mode
  169. Chip-specific AIPS-Lite information
  170. General operation
  171. Peripheral Access Control Register (AIPS_PACRn)
  172. Chip-specific DMAMUX information
  173. DMA transfers via PIT trigger
  174. DMA channels with periodic triggering capability
  175. DMA channels with no triggering capability
  176. Always-enabled DMA sources
  177. DMA Transfer Overview
  178. Memory Map/Register Definition
  179. Source Address Register (DMA_SARn)
  180. Destination Address Register (DMA_DARn)
  181. DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
  182. DMA Control Register (DMA_DCRn)
  183. Channel initialization and startup
  184. Dual-Address Data Transfer Mode
  185. Termination
  186. System Reset Status Register 0 (RCM_SRS0)
  187. System Reset Status Register 1 (RCM_SRS1)
  188. Reset Pin Filter Control register (RCM_RPFC)
  189. Reset Pin Filter Width register (RCM_RPFW)
  190. Force Mode Register (RCM_FM)
  191. Sticky System Reset Status Register 0 (RCM_SSRS0)
  192. Sticky System Reset Status Register 1 (RCM_SSRS1)
  193. Chip-specific ADC information
  194. DMA Support on ADC
  195. ADC analog supply and reference connections
  196. ADC signal descriptions
  197. Analog Channel Inputs (ADx)
  198. ADC Status and Control Registers 1 (ADCx_SC1n)
  199. ADC Configuration Register 1 (ADCx_CFG1)
  200. ADC Configuration Register 2 (ADCx_CFG2)
  201. ADC Data Result Register (ADCx_Rn)
  202. Compare Value Registers (ADCx_CVn)
  203. Status and Control Register 2 (ADCx_SC2)
  204. Status and Control Register 3 (ADCx_SC3)
  205. ADC Offset Correction Register (ADCx_OFS)
  206. ADC Plus-Side Gain Register (ADCx_PG)
  207. ADC Plus-Side General Calibration Value Register (ADCx_CLPD)
  208. ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
  209. ADC Plus-Side General Calibration Value Register (ADCx_CLP3)
  210. ADC Plus-Side General Calibration Value Register (ADCx_CLP1)
  211. ADC Minus-Side General Calibration Value Register (ADCx_CLMD)
  212. ADC Minus-Side General Calibration Value Register (ADCx_CLM4)
  213. ADC Minus-Side General Calibration Value Register (ADCx_CLM2)
  214. ADC Minus-Side General Calibration Value Register (ADCx_CLM0)
  215. Clock select and divide control
  216. Voltage reference selection
  217. Conversion control
  218. Automatic compare function
  219. Calibration function
  220. User-defined offset function
  221. Temperature sensor
  222. MCU wait mode operation
  223. MCU Low-Power Stop mode operation
  224. Initialization information
  225. Application information
  226. Sources of error
  227. Chip-specific CMP information
  228. CMP external references
  229. bit DAC key features
  230. CMP, DAC and ANMUX diagram
  231. CMP block diagram
  232. Memory map/register definitions
  233. CMP Control Register 1 (CMPx_CR1)
  234. CMP Filter Period Register (CMPx_FPR)
  235. CMP Status and Control Register (CMPx_SCR)
  236. DAC Control Register (CMPx_DACCR)
  237. CMP functional modes
  238. Power modes
  239. Startup and operation
  240. Low-pass filter
  241. CMP interrupts
  242. Digital-to-analog converter
  243. Voltage reference source select
  244. DAC Data Low Register (DACx_DATnL)
  245. DAC Status Register (DACx_SR)
  246. DAC Control Register (DACx_C0)
  247. DAC Control Register 1 (DACx_C1)
  248. DMA operation
  249. VREF Signal Descriptions
  250. VREF Trim Register (VREF_TRM)
  251. VREF Status and Control Register (VREF_SC)
  252. Voltage Reference Enabled, SC[VREFEN] = 1
  253. Internal voltage regulator
  254. MCG Control Register 1 (MCG_C1)
  255. MCG Control Register 2 (MCG_C2)
  256. MCG Status Register (MCG_S)
  257. MCG Miscellaneous Control Register (MCG_MC)
  258. LIRC divider 1
  259. MCG-Lite in Low-power mode
  260. Chip-specific OSC information
  261. OSC Signal Descriptions
  262. External Clock Connections
  263. OSC Memory Map/Register Definition
  264. OSC module modes
  265. Counter
  266. Low power modes operation
  267. Chip-specific TPM information
  268. TPM instantiation information
  269. Trigger options
  270. TPM Signal Descriptions
  271. TPM_EXTCLK — TPM External Clock
  272. Status and Control (TPMx_SC)
  273. Counter (TPMx_CNT)
  274. Modulo (TPMx_MOD)
  275. Channel (n) Status and Control (TPMx_CnSC)
  276. Channel (n) Value (TPMx_CnV)
  277. Channel Polarity (TPMx_POL)
  278. Configuration (TPMx_CONF)
  279. Prescaler
  280. Input Capture Mode
  281. Output Compare Mode
  282. Edge-Aligned PWM (EPWM) Mode
  283. Center-Aligned PWM (CPWM) Mode
  284. Registers Updated from Write Buffers
  285. Output triggers
  286. Reset Overview
  287. Chip-specific PIT information
  288. PIT/DAC triggers
  289. PIT Module Control Register (PIT_MCR)
  290. PIT Upper Lifetime Timer Register (PIT_LTMR64H)
  291. Timer Load Value Register (PIT_LDVALn)
  292. Timer Control Register (PIT_TCTRLn)
  293. Timer Flag Register (PIT_TFLGn)
  294. Interrupts
  295. Example configuration for chained timers
  296. Example configuration for the lifetime timer
  297. Chip-specific LPTMR information
  298. LPTMR prescaler/glitch filter clocking options
  299. Low Power Timer Prescale Register (LPTMRx_PSR)
  300. Low Power Timer Compare Register (LPTMRx_CMR)
  301. LPTMR prescaler/glitch filter
  302. LPTMR compare
  303. LPTMR hardware trigger
  304. Chip-specific RTC information
  305. RTC Time Seconds Register (RTC_TSR)
  306. RTC Time Alarm Register (RTC_TAR)
  307. RTC Control Register (RTC_CR)
  308. RTC Status Register (RTC_SR)
  309. RTC Lock Register (RTC_LR)
  310. RTC Interrupt Enable Register (RTC_IER)
  311. Time counter
  312. Time alarm
  313. Update mode
  314. Chip-specific USBFS information
  315. USB Power Distribution
  316. USB power management
  317. USBFS Features
  318. On-chip transceiver required external components
  319. Programmers interface
  320. USB data transfers—Receive (Rx) and Transmit (Tx)
  321. Addressing BDT entries
  322. USB transaction
  323. Peripheral ID register (USBx_PERID)
  324. Peripheral Revision register (USBx_REV)
  325. Interrupt Status register (USBx_ISTAT)
  326. Interrupt Enable register (USBx_INTEN)
  327. Error Interrupt Status register (USBx_ERRSTAT)
  328. Error Interrupt Enable register (USBx_ERREN)
  329. Status register (USBx_STAT)
  330. Control register (USBx_CTL)
  331. Address register (USBx_ADDR)
  332. Frame Number register Low (USBx_FRMNUML)
  333. BDT Page Register 2 (USBx_BDTPAGE2)
  334. Endpoint Control register (USBx_ENDPTn)
  335. USB Control register (USBx_USBCTRL)
  336. USB OTG Control register (USBx_CONTROL)
  337. USB Transceiver Control register 0 (USBx_USBTRC0)
  338. Frame Adjust Register (USBx_USBFRMADJUST)
  339. IRC48M oscillator enable register (USBx_CLK_RECOVER_IRC_EN)
  340. Clock recovery combined interrupt enable (USBx_CLK_RECOVER_INT_EN)
  341. Clock recovery separated interrupt status (USBx_CLK_RECOVER_INT_STATUS)
  342. Chip-specific SPI information
  343. SPSCK — SPI Serial Clock
  344. SPI Baud Rate Register (SPIx_BR)
  345. SPI Control Register 2 (SPIx_C2)
  346. SPI Control Register 1 (SPIx_C1)
  347. SPI Match Register low (SPIx_ML)
  348. SPI match register high (SPIx_MH)
  349. SPI data register high (SPIx_DH)
  350. SPI clear interrupt register (SPIx_CI)
  351. SPI control register 3 (SPIx_C3)
  352. Slave mode
  353. SPI FIFO Mode
  354. SPI Transmission by DMA
  355. Data Transmission Length
  356. SPI clock formats
  357. SPI baud rate generation
  358. Error conditions
  359. Low-power mode options
  360. Reset
  361. Pseudo-Code Example
  362. Chip-specific I2C information
  363. I2C Address Register 1 (I2Cx_A1)
  364. I2C Control Register 1 (I2Cx_C1)
  365. I2C Status register (I2Cx_S)
  366. I2C Data I/O register (I2Cx_D)
  367. I2C Programmable Input Glitch Filter Register (I2Cx_FLT)
  368. I2C Range Address register (I2Cx_RA)
  369. I2C Address Register 2 (I2Cx_A2)
  370. I2C SCL Low Timeout Register Low (I2Cx_SLTL)
  371. Address matching
  372. System management bus specification
  373. Resets
  374. Programmable input glitch filter
  375. DMA support
  376. Double buffering mode
  377. Chip-specific LPUART information
  378. Signal Descriptions
  379. Register definition
  380. LPUART Baud Rate Register (LPUARTx_BAUD)
  381. LPUART Status Register (LPUARTx_STAT)
  382. LPUART Control Register (LPUARTx_CTRL)
  383. LPUART Data Register (LPUARTx_DATA)
  384. LPUART Match Address Register (LPUARTx_MATCH)
  385. Transmitter functional description
  386. Receiver functional description
  387. Additional LPUART functions
  388. Interrupts and status flags
  389. Chip-specific UART information
  390. UART signal descriptions
  391. UART Baud Rate Registers: High (UARTx_BDH)
  392. UART Baud Rate Registers: Low (UARTx_BDL)
  393. UART Control Register 2 (UARTx_C2)
  394. UART Status Register 1 (UARTx_S1)
  395. UART Status Register 2 (UARTx_S2)
  396. UART Control Register 3 (UARTx_C3)
  397. UART Data Register (UARTx_D)
  398. UART Match Address Registers 1 (UARTx_MA1)
  399. UART Match Address Registers 2 (UARTx_MA2)
  400. UART Control Register 5 (UARTx_C5)
  401. UART 7816 Control Register (UARTx_C7816)
  402. UART 7816 Interrupt Enable Register (UARTx_IE7816)
  403. UART 7816 Interrupt Status Register (UARTx_IS7816)
  404. UART 7816 Wait Parameter Register (UARTx_WP7816)
  405. UART 7816 Wait FD Register (UARTx_WF7816)
  406. UART 7816 Transmit Length Register (UARTx_TL7816)
  407. UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0)
  408. UART 7816 Wait Parameter Register A (UARTx_WP7816A_T0)
  409. UART 7816 Wait Parameter Register B (UARTx_WP7816B_T0)
  410. UART 7816 Wait and Guard Parameter Register (UARTx_WGP7816_T1)
  411. Receiver
  412. Baud rate generation
  413. Data format (non ISO-7816)
  414. Single-wire operation
  415. ISO-7816/smartcard support
  416. RXEDGIF description
  417. Initialization sequence (non ISO-7816)
  418. Overrun (OR) flag implications
  419. Match address registers
  420. Chip-specific FlexIO information
  421. Version ID Register (FLEXIO_VERID)
  422. Parameter Register (FLEXIO_PARAM)
  423. FlexIO Control Register (FLEXIO_CTRL)
  424. Shifter Status Register (FLEXIO_SHIFTSTAT)
  425. Shifter Error Register (FLEXIO_SHIFTERR)
  426. Shifter Status Interrupt Enable (FLEXIO_SHIFTSIEN)
  427. Shifter Error Interrupt Enable (FLEXIO_SHIFTEIEN)
  428. Shifter Status DMA Enable (FLEXIO_SHIFTSDEN)
  429. Shifter Configuration N Register (FLEXIO_SHIFTCFGn)
  430. Shifter Buffer N Register (FLEXIO_SHIFTBUFn)
  431. Shifter Buffer N Bit Swapped Register (FLEXIO_SHIFTBUFBISn)
  432. Shifter Buffer N Bit Byte Swapped Register (FLEXIO_SHIFTBUFBBSn)
  433. Timer Configuration N Register (FLEXIO_TIMCFGn)
  434. Timer Compare N Register (FLEXIO_TIMCMPn)
  435. Timer operation
  436. Pin operation
  437. UART Receive
  438. SPI Master
  439. SPI Slave
  440. I2C Master
  441. I2S Master
  442. I2S Slave
  443. Chip-specific I2S information
  444. External signals
  445. SAI Transmit Control Register (I2Sx_TCSR)
  446. SAI Transmit Configuration 2 Register (I2Sx_TCR2)
  447. SAI Transmit Configuration 3 Register (I2Sx_TCR3)
  448. SAI Transmit Configuration 4 Register (I2Sx_TCR4)
  449. SAI Transmit Configuration 5 Register (I2Sx_TCR5)
  450. SAI Transmit Data Register (I2Sx_TDRn)
  451. SAI Receive Control Register (I2Sx_RCSR)
  452. SAI Receive Configuration 2 Register (I2Sx_RCR2)
  453. SAI Receive Configuration 3 Register (I2Sx_RCR3)
  454. SAI Receive Configuration 4 Register (I2Sx_RCR4)
  455. SAI Receive Configuration 5 Register (I2Sx_RCR5)
  456. SAI Receive Mask Register (I2Sx_RMR)
  457. SAI MCLK Control Register (I2Sx_MCR)
  458. SAI resets
  459. Synchronous modes
  460. Data FIFO
  461. Word mask register
  462. Chip-specific GPIO information
  463. GPIO signal descriptions
  464. Port Data Output Register (GPIOx_PDOR)
  465. Port Set Output Register (GPIOx_PSOR)
  466. Port Toggle Output Register (GPIOx_PTOR)
  467. Port Data Direction Register (GPIOx_PDDR)
  468. BME decorated stores
  469. BME decorated loads
  470. Additional details on decorated addresses and GPIO accesses
  471. MTB_DWT Memory Map
  472. System ROM Memory Map
  473. Glossary
  474. Flash Configuration Field Description
  475. Register Descriptions
  476. Flash Operation in Low-Power Modes
  477. Read While Write (RWW)
  478. Margin Read Commands
  479. Flash Command Description
  480. Security
  481. Reset Sequence
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This manual is suitable for:
MKL27Z128VFM4MKL27Z128VFT4MKL27Z128VLH4MKL27Z128VMP4MKL27Z256VFM4MKL27Z256VFT4MKL27Z256VLH4MKL27Z256VMP4
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