write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) whenS[SPTEF] is set, the SPI data registers can be written automatically by DMA withoutreading the S register first.Data may be read from the SPI data registers any time after S[SPRF] is set and beforeanother transfer is finished. Failure to read the data out of the receive data buffer before anew transfer ends causes a receive overrun condition, and the data from the new transferis lost. The new data is lost because the receive buffer still held the previous characterand was not ready to accept the new data. There is no indication for a receive overruncondition, so the application system designer must ensure that previous data has beenread from the receive buffer before a new transfer is initiated.In 8-bit mode, only the DL register is available. Reads of the DH register return all zeros.Writes to the DH register are ignored.In 16-bit mode, reading either byte (the DH or DL register) latches the contents of bothbytes into a buffer where they remain latched until the other byte is read. Writing toeither byte (the DH or DL register) latches the value into a buffer. When both bytes havebeen written, they are transferred as a coherent 16-bit value into the transmit data buffer.Address: Base address + 6h offsetBit 7 6 5 4 3 2 1 0Read Bits[7:0]WriteReset 0 0 0 0 0 0 0 0SPIx_DL field descriptionsField DescriptionBits[7:0] Data (low byte)35.4.8 SPI data register high (SPIx_DH)Refer to the description of the DL register.Address: Base address + 7h offsetBit 7 6 5 4 3 2 1 0Read Bits[15:8]WriteReset 0 0 0 0 0 0 0 0SPIx_DH field descriptionsField DescriptionBits[15:8] Data (high byte)Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016584 Freescale Semiconductor, Inc.
