SPIx_C1 field descriptions (continued)Field Description3CPOLClock PolaritySelects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modulesmust have identical CPOL values.This bit effectively places an inverter in series with the clock signal either from a master SPI device or to aslave SPI device. Refer to the description of “SPI Clock Formats” for details.0 Active-high SPI clock (idles low)1 Active-low SPI clock (idles high)2CPHAClock PhaseSelects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer to thedescription of “SPI Clock Formats” for details.0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer.1 First edge on SPSCK occurs at the start of the first cycle of a data transfer.1SSOESlave Select Output EnableThis bit is used in combination with the Mode Fault Enable (MODFEN) field in the C2 register and theMaster/Slave (MSTR) control bit to determine the function of the SS pin.0 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slavemode, SS pin function is slave select input.When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode,SS pin function is slave select input.1 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slavemode, SS pin function is slave select input.When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SSpin function is slave select input.0LSBFELSB First (shifter direction)This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the dataregister always have the MSB in bit 7 (or bit 15 in 16-bit mode).0 SPI serial data transfers start with the most significant bit.1 SPI serial data transfers start with the least significant bit.35.4.5 SPI Match Register low (SPIx_ML)This register, together with the MH register, contains the hardware compare value. Whenthe value received in the SPI receive data buffer equals this hardware compare value, theSPI Match Flag in the S register (S[SPMF]) sets.In 8-bit mode, only the ML register is available. Reads of the MH register return allzeros. Writes to the MH register are ignored.Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016582 Freescale Semiconductor, Inc.
