Table 7-1. Chip power modes (continued)Chip mode Description Core mode NormalrecoverymethodNOTE: The LLWU interrupt must not be masked bythe interrupt controller to avoid a scenariowhere the system does not fully exit stopmode on an LLS recovery• All SRAM is operating (content retained and I/O states held).VLLS3 (VeryLow-LeakageStop3)• Most peripherals are disabled (with clocks stopped), but OSC,LLWU, LPTMR, RTC, CMP can be used.• NVIC is disabled; LLWU is used to wake up.• SRAM_U and SRAM_L remain powered on (content retainedand I/O states held).Sleep Deep Wake-up Reset2VLLS1 (VeryLow-LeakageStop1)• Most peripherals are disabled (with clocks stopped), but OSC,LLWU, LPTMR, RTC, CMP can be used.• NVIC is disabled; LLWU is used to wake up.• All of SRAM_U and SRAM_L are powered off.• The 32-byte system register file remains powered for customer-critical dataSleep Deep Wake-up Reset2VLLS0 (VeryLow-LeakageStop 0)• Most peripherals are disabled (with clocks stopped), but LLWU,LPTMR, RTC can be used.• NVIC is disabled; LLWU is used to wake up.• All of SRAM_U and SRAM_L are powered off.• The 32-byte system register file remains powered for customer-critical data• LPO disabled, optional POR brown-out detectionSleep Deep Wake-up Reset21. Resumes Normal Run mode operation by executing the LLWU interrupt service routine.2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.7.4 Entering and exiting power modesThe WFI instruction invokes wait and stop modes for the chip. The processor exits thelow-power mode via an interrupt.For LLS and VLLS modes, the wake-up sources are limited to LLWU generated wake-ups,NMI_b pin, or RESET_b pin assertions. When the NMI_b pin or RESET_b pin havebeen disabled through associated FTFA_FOPT settings, then these pins are ignored aswakeup sources. The wake-up flow from VLLSx is always through reset.NOTEThe WFE instruction can have the side effect of entering a low-power mode, but that is not its intended usage. See ARMdocumentation for more on the WFE instruction.On VLLS recoveries, the I/O pins continue to be held in a static state after code executionbegins, allowing software to reconfigure the system before unlocking the I/O. RAM isretained in VLLS3 only.Chapter 7 Power ManagementKL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 95
