RTC_TPR field descriptionsField Description31–16ReservedThis field is reserved.This read-only field is reserved and always has the value 0.TPR Time Prescaler RegisterWhen the time counter is enabled, the TPR is read only and increments every 32.768 kHz clock cycle. Thetime counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, theTPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic oneto a logic zero.32.3.3 RTC Time Alarm Register (RTC_TAR)Address: 4003_D000h base + 8h offset = 4003_D008hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R TARWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RTC_TAR field descriptionsField DescriptionTAR Time Alarm RegisterWhen the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] andthe TSR[TSR] increments. Writing to the TAR clears the SR[TAF].32.3.4 RTC Time Compensation Register (RTC_TCR)Address: 4003_D000h base + Ch offset = 4003_D00ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R CIC TCV CIR TCRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RTC_TCR field descriptionsField Description31–24CICCompensation Interval CounterCurrent value of the compensation interval counter. If the compensation interval counter equals zero thenit is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once asecond.23–16TCVTime Compensation ValueTable continues on the next page...Register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016516 Freescale Semiconductor, Inc.
