FLEXIO_TIMCFGn field descriptions (continued)Field Description5–4TSTOPTimer Stop BitThe stop bit can be added on a timer compare (between each word) or on a timer disable. When stop bit isenabled, configured shifters will output the contents of the stop bit when the timer is disabled. When stopbit is enabled on timer disable, the timer remains disabled until the next rising edge of the shift clock. Ifconfigured for both timer compare and timer disable, only one stop bit is inserted on timer disable.00 Stop bit disabled01 Stop bit is enabled on timer compare10 Stop bit is enabled on timer disable11 Stop bit is enabled on timer compare and timer disable3–2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1TSTARTTimer Start BitWhen start bit is enabled, configured shifters will output the contents of the start bit when the timer isenabled and the timer counter will reload from the compare register on the first rising edge of the shiftclock.0 Start bit disabled1 Start bit enabled0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.39.3.19 Timer Compare N Register (FLEXIO_TIMCMPn).Address: 4005_F000h base + 500h offset + (4d × i), where i=0d to 3dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 CMPWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FLEXIO_TIMCMPn field descriptionsField Description31–16ReservedThis field is reserved.This read-only field is reserved and always has the value 0.CMP Timer Compare ValueThe timer compare value is loaded into the timer counter when the timer is first enabled, when the timer isreset and when the timer decrements down to zero. In dual 8-bit counters baud/bit mode, the lower 8-bitsconfigures the baud rate divider equal to (CMP[7:0] + 1) * 2. The upper 8-bits configure the number of bitsin each word equal to (CMP[15:8] + 1) / 2. In dual 8-bit counters PWM mode, the lower 8-bits configure thehigh period of the output to (CMP[7:0] + 1) and the upper 8-bits configure the low period of the output to(CMP[15:8] + 1). In 16-bit counter mode, the compare value can be used to generate the baud rate divider(if shift clock source is timer output) to equal (CMP[15:0] + 1) * 2. When the shift clock source is a pin orTable continues on the next page...Memory Map and RegistersKL27 Sub-Family Reference Manual , Rev. 5, 01/2016766 Freescale Semiconductor, Inc.
