40.4.12 SAI Receive Configuration 5 Register (I2Sx_RCR5)This register must not be altered when RCSR[RE] is set.Address: 4002_F000h base + 94h offset = 4002_F094hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 WNW 0 W0W 0 FBT 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2Sx_RCR5 field descriptionsField Description31–29ReservedThis field is reserved.This read-only field is reserved and always has the value 0.28–24WNWWord N WidthConfigures the number of bits in each word, for each word except the first in the frame. The value writtenmust be one less than the number of bits per word. Word width of less than 8 bits is not supported.23–21ReservedThis field is reserved.This read-only field is reserved and always has the value 0.20–16W0WWord 0 WidthConfigures the number of bits in the first word in each frame. The value written must be one less than thenumber of bits in the first word. Word width of less than 8 bits is not supported if there is only one word perframe.15–13ReservedThis field is reserved.This read-only field is reserved and always has the value 0.12–8FBTFirst Bit ShiftedConfigures the bit index for the first bit received for each word in the frame. If configured for MSB First, theindex of the next bit received is one less than the current bit received. If configured for LSB First, the indexof the next bit received is one more than the current bit received. The value written must be greater than orequal to the word width when configured for MSB First. The value written must be less than or equal to 31-word width when configured for LSB First.Reserved This field is reserved.This read-only field is reserved and always has the value 0.40.4.13 SAI Receive Data Register (I2Sx_RDRn)Reading this register introduces one additional peripheral clock wait state on each read.Address: 4002_F000h base + A0h offset + (4d × i), where i=0d to 0dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R RDRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 40 Synchronous Audio Interface (SAI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 809
