I2Sx_RCSR field descriptions (continued)Field Description4–2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1FWDEFIFO Warning DMA EnableEnables/disables DMA requests.0 Disables the DMA request.1 Enables the DMA request.0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.40.4.9 SAI Receive Configuration 2 Register (I2Sx_RCR2)This register must not be altered when RCSR[RE] is set.Address: 4002_F000h base + 88h offset = 4002_F088hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R SYNC BCS BCI MSEL BCP BCD 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 DIVWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2Sx_RCR2 field descriptionsField Description31–30SYNCSynchronous ModeConfigures between asynchronous and synchronous modes of operation. When configured for asynchronous mode of operation, the transmitter must be configured for asynchronous operation.00 Asynchronous mode.01 Synchronous with transmitter.10 Synchronous with another SAI receiver.11 Synchronous with another SAI transmitter.29BCSBit Clock SwapThis field swaps the bit clock used by the receiver. When the receiver is configured in asynchronous modeand this bit is set, the receiver is clocked by the transmitter bit clock (SAI_TX_BCLK). This allows thetransmitter and receiver to share the same bit clock, but the receiver continues to use the receiver framesync (SAI_RX_SYNC).When the receiver is configured in synchronous mode, the transmitter BCS field and receiver BCS fieldmust be set to the same value. When both are set, the transmitter and receiver are both clocked by thereceiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync (SAI_TX_SYNC).Table continues on the next page...Memory map and register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016804 Freescale Semiconductor, Inc.
