11.7.2 Global Pin Control Low Register (PORTx_GPCLR)Only 32-bit writes are supported to this register.Address: Base address + 80h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0W GPWE GPWDReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PORTx_GPCLR field descriptionsField Description31–16GPWEGlobal Pin Write EnableSelects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD.0 Corresponding Pin Control Register is not updated with the value in GPWD.1 Corresponding Pin Control Register is updated with the value in GPWD.GPWD Global Pin Write DataWrite value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.11.7.3 Global Pin Control High Register (PORTx_GPCHR)Only 32-bit writes are supported to this register.Address: Base address + 84h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0W GPWE GPWDReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PORTx_GPCHR field descriptionsField Description31–16GPWEGlobal Pin Write EnableSelects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD.0 Corresponding Pin Control Register is not updated with the value in GPWD.1 Corresponding Pin Control Register is updated with the value in GPWD.GPWD Global Pin Write DataWrite value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.Memory map and register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016138 Freescale Semiconductor, Inc.
